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Verilog
Verilog is a widely-used hardware description language (HDL) that enables designers to model, simulate, and synthesize digital circuits. It provides a text-based format for specifying the structure and behavior of electronic systems, making it easier to design complex hardware components such as microprocessors, memory, and communication devices.
- GitHub: https://github.com/topics/verilog
- Wikipedia: https://en.wikipedia.org/wiki/Verilog
- Aliases: hdl, hardware-description-language,
- Last updated: 2025-01-24 00:33:21 UTC
- JSON Representation
https://github.com/mohammadmahdi-abdolhosseini/computer-architecture-lab
Computer Architecture Lab - Assignments - Fall 2023
arm-processor fpga modelsim quartus2 systemverilog verilog vhdl
Last synced: 07 Jan 2025
https://github.com/arsham-lh/computer-architecture
Code files related to the Computer Architecture course, taught by M. Movahedin
computer-architecture mips-assembly multi-cycle-processor single-cycle-processor verilog
Last synced: 17 Jan 2025
https://github.com/ain1084/audio_level_meter
This is an audio level meter implemented using Verilog HDL.
audio machxo2 verilog visualization
Last synced: 20 Dec 2024
https://github.com/gcerpa01/compe470
Work of my projects I worked on while enrolled in SDSU's COMPE470 Digital Circuits course in Spring 2023
Last synced: 17 Jan 2025
https://github.com/akafael/verilog-sandbox
selflearning tutorial-exercises verilog
Last synced: 29 Nov 2024
https://github.com/cepdnaclk/e18-co502-rv32im-pipeline-implementation-group4
Single-cycle MIPS-like processor with a memory subsystem including a cache.
computer-architecture risc-v verilog
Last synced: 11 Jan 2025
https://github.com/roscibely/arithmetic-logic-unit
A simple arithmetic logic unit (ALU) with System verilog
Last synced: 21 Jan 2025
https://github.com/dpieve/university
A resource for students learning programming and personal reference.
assembly cpp haskell haskell-exercises java matlab prolog python shell unifei-university verilog
Last synced: 22 Dec 2024
https://github.com/sergz72/fpga
FPGA related stuff
assembler assembly-language bytecode-compiler cpu cyclone forth forth-cpu forth-language fpga fpga-programming gowin java java-cpu risc-v verilog
Last synced: 28 Nov 2024
https://github.com/dyna-bytes/fpga_winter_internship_2020
[Korea University Elementary Particle Physics Lab] Hardware control research using FPGA
Last synced: 02 Dec 2024
https://github.com/dyna-bytes/fisr
Specialized FPU for Fast Inverse Square Root Algorithm
Last synced: 02 Dec 2024
https://github.com/chili-chips-ba/uberclock
Digital systems are clocked. This project is about constructed a high-Q clock by simmering an ordinary quartz in a heavy numerical "secret sauce" that is fully open to the public.
clock-generator crystal dsp fpga risc-v rtl stratum-2 verilog
Last synced: 06 Dec 2024
https://github.com/kaushalmodi/nim-svvpi
Wrapper for SystemVerilog VPI headers sv_vpi_user.h and vpi_user.h
1364-2005 1800-2017 nim pli systemverilog verilog vpi
Last synced: 16 Jan 2025
https://github.com/birdybro/nand2tetris_mister
Nand2Tetris for MiSTer (as a learning experience for me).
hdl mister misterfpga tetris verilog verilog-hdl
Last synced: 05 Dec 2024
https://github.com/ethanuppal/berkeley-hardfloat
Downstream hardfloat with custom patches
berkeley floating-point verilog
Last synced: 14 Dec 2024
https://github.com/niqzart/pylohd
High-level framework for simplification and systematization of processes in electronic design
converter hdl python thesis-project verilog
Last synced: 06 Dec 2024
https://github.com/paulchen2713/introduction_to_veriloghdl
Digital System Design Course Practices
Last synced: 23 Jan 2025
https://github.com/cr0a3/hardwarelib
A libary to create asics in short time
Last synced: 23 Jan 2025
https://github.com/kenny2github/verilog-cpu
A very rudimentary and haphazard CPU created in Verilog.
Last synced: 20 Dec 2024
https://github.com/polaris000/cs_f342
Lab assignments and some practise done for the Computer Architecture course at BITS Pilani
assembly bits-pilani comparch computer-architecture labs practise verilog
Last synced: 09 Jan 2025
https://github.com/guntas-13/verilog
Compilation of all the Verilog Assignments in the course ES204 - Digital Systems (Spring 2024) - Prof. Joycee Mekie
Last synced: 03 Dec 2024
https://github.com/yasnakateb/blinky
💡A Quartus II project testing the functionality of the Altera Cyclone IV EP4CE6E22C8N board
altera-fpga fpga verilog verilog-hdl
Last synced: 20 Jan 2025
https://github.com/davoodeh/verilog2hspice
Do some simple conversions on Verilog files to make them compatible with HSpice
Last synced: 15 Dec 2024
https://github.com/risto97/socmake
Build system for RTL and SoC designs
cmake cpu hardware rtl simulation systemc systemonchip systemrdl verilog
Last synced: 21 Dec 2024
https://github.com/orcalinux/computer-organization-and-architecture
Verilog code examples and materials for Computer Organization.
8086-microprocessor computer-architecture computer-organization modelsim pic programmable-interrupt-controller qu synthesis-project verilog
Last synced: 20 Dec 2024
https://github.com/kulp/tappy
tappy is a tiny Verilog driver for PS/2 keyboards, for use in FPGAs
Last synced: 16 Dec 2024
https://github.com/davidf1000/sistemdigital_vhdl
Final Project for Digital System Lab. Flappy Bird Imitation Game created using VHDL for FPGA DE1.
Last synced: 11 Jan 2025
https://github.com/shishir-dey/pcb-dev-fpga-ice40
A 2 layer development board with a Lattice Semiconductor ICE40UP5K-SG48ITR FPGA. Made with KiCad
development-board fpga hardware pcb-design verilog
Last synced: 14 Jan 2025
https://github.com/yasnakateb/threshold
🖼✏️ My first baby steps into the world of image processing
grayscale image-processing threshold verilog verilog-hdl xilinx-ise
Last synced: 20 Jan 2025
https://github.com/shpegun60/open_std_fpga
This std libraries on fpga
fpga-std standard-library-fpga verilog
Last synced: 18 Jan 2025
https://github.com/et312/custom_cpu
Custom 16-bit RISC-based CPU with custom control unit, ALU, and memory block designs
Last synced: 16 Dec 2024
https://github.com/sofiavalos/verilog_ethernet_10g_mac
Bloques y bancos de pruebas MAC para Ethernet 10G.
Last synced: 12 Dec 2024
https://github.com/j-m-li/logical16x16
Hardware Description Language for EPROM and FLASH memories
Last synced: 18 Nov 2024
https://github.com/susiejojo/sobel_filter
Sobel filter for edge detection in images supporting parallel processing using Verilog on Xilinx ISE 13.4
hdl sobel-filter verilog xilinx-ise
Last synced: 17 Dec 2024
https://github.com/ewdlop/verilog-notes
HDLBit-Pratice. https://hdlbits.01xz.net/wiki/Main_Page
combinational-logic finte-state-machine flip-flops sequential-logic verilog
Last synced: 27 Dec 2024
https://github.com/wassimhedfi/fpga_adc_pwm_motorcontrol
This repository contains the implementation of a motor speed control system using an FPGA. The speed is adjusted dynamically through a potentiometer, leveraging ADC for analog-to-digital conversion and PWM for precise motor control.
adc de10-lite fpga html motor-speed pwm verilog vhdl
Last synced: 04 Dec 2024
https://github.com/princeranjan03/imageencryption_i-chip
This project focuses on creating a hardware-based encryption and decryption system that implements the Data Encryption Standard (DES) algorithm.
cipher cryptography data-encryption data-encryption-standard encoding encryption-decryption fpga image image-processing opencv rtldesign source-coding verilog verilog-hdl verilog-project vivado xilinx xilinx-vivado
Last synced: 04 Dec 2024
https://github.com/mssola/hdl
Playing around with Hardware Description Languages.
Last synced: 29 Nov 2024
https://github.com/memgonzales/hdl-flip-flop
Compilation of Verilog behavioral models and test benches for the four types of flip-flops (SR, JK, D, and T)
behavioral-modeling computer-architecture flip-flop sequential-circuits verilog
Last synced: 20 Jan 2025