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RISC-V

Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use. A number of companies are offering or have announced RISC-V hardware, open source operating systems with RISC-V support are available and the instruction set is supported in several popular software toolchains.

Notable features of the RISC-V ISA include a load–store architecture, bit patterns to simplify the multiplexers in a CPU, IEEE 754 floating-point, a design that is architecturally neutral, and placing most-significant bits at a fixed location to speed sign extension. The instruction set is designed for a wide range of uses. The base instruction set has a fixed length of 32-bit naturally aligned instructions, and the ISA supports variable length extensions where each instruction could be an any number of 16-bit parcels in length. Subsets support small embedded systems, personal computers, supercomputers with vector processors, and warehouse-scale 19 inch rack-mounted parallel computers.

GitHub: https://github.com/topics/riscv
Wikipedia: https://en.wikipedia.org/wiki/riscv
Aliases: risc-v, riscv-cpu, riscv-core,
Last updated: 2024-11-04 00:26:05 UTC
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https://github.com/max22-/rv32

RISC-V (32-bit) emulator, in C89

c89 emulator risc-v risc-v-emulator riscv simulator

Last synced: 12 Oct 2024

https://github.com/zhayujie/minos

A minimal viable operating system.

c os riscv

Last synced: 16 Oct 2024

https://github.com/lebrancconvas/typescript-for-concept

Clarify anything I'm interested in TypeScript until It can't. (Because TypeScript is good and fit to me for mapping out the domain).

computer-architecture cpu digital-circuit fpga fpga-programming low-byte-productions low-level memory playground-project risc-v riscv typescript virtual-machine vm

Last synced: 11 Nov 2024

https://github.com/sekky61/riscv-sim

Web-based RISC-V superscalar simulator

java nextjs react riscv

Last synced: 08 Nov 2024

https://github.com/risceirb/risc-v-processor

Processor RISC-V and application

assembly assembly-risc assembly-risc-v branch-predictor enseirb enseirb-matmeca modelsim monocycle-processor pipeline pipeline-processor processor risc-v risc-v-architecture risc-v-architectures risc-v-assembly riscv ufsm

Last synced: 12 Oct 2024

https://github.com/coastalwhite/pulpino-top-level-cw305

The top-level Verilog files for the CW305 to run and communicate with the RISC-V PULPINO core

chipwhisperer pulpino riscv

Last synced: 13 Oct 2024

https://github.com/xigh/rvdis-rs

RISCV RV32/64 very simple disassembler with ELF support

disassembler risc-v riscv rust

Last synced: 10 Nov 2024

https://github.com/rmacnak/riscv-tools

RISC-V assembler, disassembler and simulator suitable for a JIT.

jit riscv

Last synced: 12 Oct 2024

https://github.com/carlosedp/rvasmweb

An experimental RISC-V Assembler web app built on Scala.js

assembler fpga riscv scala scalajs

Last synced: 27 Oct 2024

https://github.com/evanluo42/phakel-os

xv6 RISC-V Written in Rust

os riscv rust xv6

Last synced: 02 Nov 2024

https://github.com/zilleali/riscv

assembly cpp riscv riscv32

Last synced: 12 Oct 2024

https://github.com/ahmedheakl/asm2asm

From CISC to RISC: Language-Model Guided Assembly Transpilation

arm64 assembly assembly-benchmark evaluation llm riscv training transpilation

Last synced: 04 Nov 2024

https://github.com/justxuewei/project-rcore

Yet another rCore implementation by justxuewei

os rcore riscv rust

Last synced: 16 Oct 2024

https://github.com/jasonbrave/microsoc

RISC-V SoC

microcontroller risc-v riscv soc system-on-chip systemverilog uart verilog

Last synced: 02 Nov 2024

https://github.com/doubleshotgun/rasm

Making assembly easier with Rasm

assembler assembly c nelua risc-v risc-v64 riscv riscv64

Last synced: 12 Oct 2024

https://github.com/cepdnaclk/e16-co502-rv32im-noc-implementation

noc riscv

Last synced: 12 Nov 2024

https://github.com/m-tmatma/riscv-yocto

build environment for https://github.com/riscv/meta-riscv

riscv yocto

Last synced: 07 Nov 2024

https://github.com/shiritai/aias-lab6-spring-2024

Lab6 of AI computing Architecture and System (2024 spring) around riscv emulator and implementation of fibonacci, sudoku (2x2) and maxpool in RISC-V

assembly fibonacci maxpool2d riscv riscv-emulator sudoku

Last synced: 08 Nov 2024

https://github.com/skpro-glitch/shorthand-risc

This is a simplified assembly language with a tabular structured instruction set. This is meant for easy learning and fast implementation of assembly languages in microprocessors and microcontrollers. - Soham Kapur, VIT Chennai

assembler assembly assembly-language assembly-language-programming compiler compiler-construction compiler-design compiler-optimization compiler-principles compilers risc risc-processor risc-v riscv shorthand shorthand-notation shorthand-syntax

Last synced: 12 Oct 2024

https://github.com/penberg/riscv-rs

Yet another RISC-V emulator written in Rust.

riscv riscv-emulator rust

Last synced: 13 Oct 2024

https://github.com/jlkiri/pathos

A simple OS that runs on the RISC-V architecture.

os riscv rust

Last synced: 15 Oct 2024

https://github.com/trmckay/docker-rust-riscv

Rust, GNU, and QEMU toolchains for riscv64 and riscv32

docker riscv rust

Last synced: 12 Oct 2024

https://github.com/tmahlburg/mriscv

simple, modular rv32i implementation (WIP)

risc-v riscv riscv32 rv32i verilog verilog-hdl

Last synced: 12 Oct 2024

https://github.com/calint/tang-nano-20k--riscv

riscv rv32i tang-nano-20k verilog

Last synced: 11 Nov 2024

https://github.com/muhammadtalhasami/riscv-assembly

This repo is the learning journey of the riscv assembly language. you will learn how to write the high level code in to the riscv assembly code.

high-level-language riscv riscv-assembly riscv-assembly-language riscv32 riscv64 spike spike-simulator venus venus-simulator venus-simulator-riscv

Last synced: 06 Nov 2024

https://github.com/the-pinbo/risc-spm

This project involves the development and enhancement of a RISC Stored-Program Machine (RISC SPM), based on the architecture detailed in "Advanced Digital Design with the Verilog HDL" by Michael D. Ciletti.

computer-architecture riscv verilog

Last synced: 06 Nov 2024