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RISC-V
Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use. A number of companies are offering or have announced RISC-V hardware, open source operating systems with RISC-V support are available and the instruction set is supported in several popular software toolchains.
Notable features of the RISC-V ISA include a load–store architecture, bit patterns to simplify the multiplexers in a CPU, IEEE 754 floating-point, a design that is architecturally neutral, and placing most-significant bits at a fixed location to speed sign extension. The instruction set is designed for a wide range of uses. The base instruction set has a fixed length of 32-bit naturally aligned instructions, and the ISA supports variable length extensions where each instruction could be an any number of 16-bit parcels in length. Subsets support small embedded systems, personal computers, supercomputers with vector processors, and warehouse-scale 19 inch rack-mounted parallel computers.
- GitHub: https://github.com/topics/riscv
- Wikipedia: https://en.wikipedia.org/wiki/riscv
- Aliases: risc-v, riscv-cpu, riscv-core,
- Last updated: 2024-07-29 13:56:57 UTC
- JSON Representation
https://github.com/rustsbi/sbi-spec
Definitions and constants in RISC-V Supervisor Binary Interface (RISC-V SBI)
Last synced: 02 Aug 2024
https://github.com/kkinos/grvemu
RISC-V emulator for CLI written in Go.
cli emulator go riscv riscv-emulator
Last synced: 02 Aug 2024
https://github.com/deadsy/rvda
RISC-V Disassembler
disassembler go golang risc-v riscv
Last synced: 02 Aug 2024
https://github.com/jiegec/riscv-toolchain
Build bleeding edge riscv toolchain in Docker
Last synced: 02 Aug 2024
https://github.com/hexdae/toolchains_riscv_gnu
RISC-V bazel rules for GCC compilation
bare-metal bazel gcc riscv toolchain
Last synced: 05 Aug 2024
https://github.com/d901203/rv2llvm
Static Binary Translator RISC-V to LLVM IR
binary-translation elf go golang llvm llvm-ir risc-v riscv
Last synced: 02 Aug 2024