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RISC-V
Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use. A number of companies are offering or have announced RISC-V hardware, open source operating systems with RISC-V support are available and the instruction set is supported in several popular software toolchains.
Notable features of the RISC-V ISA include a load–store architecture, bit patterns to simplify the multiplexers in a CPU, IEEE 754 floating-point, a design that is architecturally neutral, and placing most-significant bits at a fixed location to speed sign extension. The instruction set is designed for a wide range of uses. The base instruction set has a fixed length of 32-bit naturally aligned instructions, and the ISA supports variable length extensions where each instruction could be an any number of 16-bit parcels in length. Subsets support small embedded systems, personal computers, supercomputers with vector processors, and warehouse-scale 19 inch rack-mounted parallel computers.
- GitHub: https://github.com/topics/riscv
- Wikipedia: https://en.wikipedia.org/wiki/riscv
- Aliases: risc-v, riscv-cpu, riscv-core,
- Last updated: 2024-12-18 00:26:47 UTC
- JSON Representation
https://github.com/pulp-platform/hero
Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and an application-class host CPU, including full-stack software and hardware.
computer-architecture fpga heterogeneous-computing heterogeneous-parallel-programming iommu many-core-architectures openmp-offloading openmp-parallelization riscv shared-memory unified-virtual-memory
Last synced: 03 Nov 2024
https://github.com/zyedidia/multiplix
An operating system kernel for RISC-V and AArch64 SBCs
aarch64 bare-metal dlang kernel operating-system osdev raspberry-pi riscv
Last synced: 15 Nov 2024
https://github.com/ittuann/enterprise_e
第十六届智能车竞赛-国家级一等奖-嵌入式控制开源(恩智浦杯/飞思卡尔杯)-全国第14名 🏆
board embedded embedded-c freescale-cup hardware intelligent-car nxp-cup pid riscv smart-car wch
Last synced: 09 Nov 2024
https://github.com/howardlau1999/yatcpu
Yet another toy CPU.
chisel-generator chisel3 cpu risc-v riscv
Last synced: 30 Nov 2024
https://github.com/xuantie-rv/csi-nn2
An optimized neural network operator library for chips base on Xuantie CPU.
deep-learning inference-engine neural-network risc-v riscv riscv-assembly
Last synced: 13 Dec 2024
https://github.com/pulp-platform/pulp_soc
pulp_soc is the core building component of PULP based SoCs
Last synced: 09 Nov 2024
https://github.com/sifive/riscvspecformal
The RiscvSpecKami package provides SiFive's RISC-V processor model. Built using Coq, this processor model can be used for simulation, model checking, and semantics analysis. The RISC-V processor model can be output as Verilog and simulated/synthesized using standard Verilog tools.
coq formal-verification hardware hardware-designs riscv riscv-simulator
Last synced: 12 Oct 2024
https://github.com/lupyuen/lupyuen.github.io
Lup Yuen's Articles and Resume
allwinner-a64 bl602 bl604 cortex embedded grafana iot lora lorawan mynewt nuttx pinephone prometheus quectel riscv roblox rust thethingsnetwork
Last synced: 14 Nov 2024
https://github.com/seldridge/rocket-rocc-examples
Tests for example Rocket Custom Coprocessors
Last synced: 08 Nov 2024
https://github.com/mmicko/fpga101-workshop
FPGA 101 - Workshop materials
apio fpga hackaday icestorm icestudio micropython riscv verilog
Last synced: 08 Nov 2024
https://github.com/riscv-rust/k210-hal
Rust's hardware abstract layer (HAL) for K210 chip, a dual RV64GC SoC with hardware accelerated AI peripherals. Contributions welcomed!
embedded-hal k210 kendryte riscv rust rust-embedded
Last synced: 05 Nov 2024
https://github.com/nuclei-software/nmsis
Nuclei Microcontroller Software Interface Standard Development Repo
aiot dsp embedded embedded-software iot iot-platform micro-controllers nmsis nn nuclei risc-v riscv
Last synced: 01 Dec 2024
https://github.com/racerxdl/riscv-emulator
Golang RISC-V emulator that can play DOOM
doom emulator golang risc-v riscv toy-emulator
Last synced: 07 Nov 2024
https://github.com/dot-asm/cryptogams
CRYPTOGAMS distribution repository
aes-cipher aes-ni arm arm64 assembly avx512 chacha20-poly1305 constant-time cryptography keccak mips ppc riscv sha1 sha256 sha3 sha512 systemz x86 x86-64
Last synced: 03 Dec 2024
https://github.com/misyltoad/riscv-vscript
A port of mini-rv32ima to VScript (Squirrel 3)
risc-v riscv rv32ima small source-engine squirrel squirrel-lang team-fortress-2 tf2 valve-games vscript
Last synced: 13 Nov 2024
https://github.com/openmachine-ai/tinyfive
TinyFive is a lightweight RISC-V emulator and assembler written in Python with neural network examples
ai assembler assembly compiler machine-learning ml risc-v risc-v-32-simulation risc-v-simulator riscv riscv-asm riscv-assembler riscv-assembly riscv-emulator riscv-simulator riscv32
Last synced: 16 Nov 2024
https://github.com/OpenMachine-ai/tinyfive
TinyFive is a lightweight RISC-V emulator and assembler written in Python with neural network examples
ai assembler assembly compiler machine-learning ml risc-v risc-v-32-simulation risc-v-simulator riscv riscv-asm riscv-assembler riscv-assembly riscv-emulator riscv-simulator riscv32
Last synced: 17 Nov 2024
https://github.com/IBM/rocc-software
C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)
Last synced: 09 Nov 2024
https://github.com/kuangjux/hypocaust-2
hypocaust-2, a type-1 hypervisor with H extension run on RISC-V machine
Last synced: 28 Oct 2024
https://github.com/kuangjux/hypocaust
hypocaust, a S-mode trap and emulate type-1 hypervisor run on RISC-V machine.
Last synced: 28 Oct 2024
https://github.com/KuangjuX/hypocaust
hypocaust, a S-mode trap and emulate type-1 hypervisor run on RISC-V machine.
Last synced: 11 Nov 2024
https://github.com/64kramsystem/qemu-pinning
My QEMU fork with pinning (affinity) support and a few tweaks.
hypervisor qemu risc-v riscv virtualization
Last synced: 19 Dec 2024
https://github.com/dtcxzyw/cmmc
An unofficial reference implementation of the C Minus Minus Compiler
armv7 compiler compiler-design compiler-principles mips32 optimization-compiler riscv
Last synced: 28 Oct 2024
https://github.com/racerxdl/riscv-online-asm
RISC-V Online Assembler using Emscripten, Gnu Binutils
assembler assembly binutils gas risc-v risc-v-assembly riscv
Last synced: 07 Nov 2024
https://github.com/lioncash/biscuit
A runtime code generator for RISC-V
assembly code-generation cpp risc-v riscv
Last synced: 28 Oct 2024
https://github.com/microdynamics-cpu/tree-core-cpu
:deciduous_tree: A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.
chisel cpu processor riscv rt-thread rtl scala softcore verilator
Last synced: 28 Nov 2024
https://github.com/noteed/riscv-hello-asm
Bare metal RISC-V assembly hello world
Last synced: 18 Nov 2024
https://github.com/michaeljclark/riscv-meta
RISC-V Instruction Set Metadata
Last synced: 05 Nov 2024
https://github.com/rustsbi/rustsbi-k210
Kendryte K210 SBI support using RustSBI, provides privileged spec 1.12 environment by emulating it using 1.9.1
riscv rust rust-embedded rustsbi sbi
Last synced: 09 Nov 2024
https://github.com/MaxXSoft/GeeOS
The Gee (寂) Operating System, written in YuLang.
operating-system osdev riscv yulang
Last synced: 11 Nov 2024
https://github.com/schorrm/arm2riscv
Arm AArch64 to RISC-V Transpiler
aarch64 arm64 armv8 asm risc risc-v risc-v-assembly risc-v64 riscv riscv-asm riscv-assembly riscv64 rv64gc transpiler
Last synced: 08 Nov 2024
https://github.com/nmeum/zig-riscv-embedded
Experimental Zig-based CoAP node for the HiFive1 RISC-V board
bare-metal coap coap-server embedded hifive1 risc-v riscv zig
Last synced: 06 Nov 2024
https://github.com/ibm/ace-riscv
Assured confidential execution (ACE) implements VM-based trusted execution environment (TEE) for RISC-V with focus on a formally verified and auditable security monitor.
confidential-computing coq formal-verification refinedrust riscv rust-lang security trusted-computing trusted-execution-environment virtualization
Last synced: 12 Nov 2024
https://github.com/lupyuen/tcc-riscv32-wasm
TCC (Tiny C Compiler) for 64-bit RISC-V, compiled to WebAssembly with Zig Compiler
nuttx riscv riscv64 romfs tcc webassembly zig ziglang
Last synced: 30 Sep 2024
https://github.com/jserv/rv32jit
JIT-accelerated RISC-V instruction set simulator
dynamic-binary-translation jit-compiler risc-v riscv riscv-emulator riscv-simulator riscv32
Last synced: 10 Nov 2024
https://github.com/platformio/platform-shakti
Shakti: development platform for PlatformIO
platformio platformio-platform risc risc-v riscv
Last synced: 07 Oct 2024
https://github.com/stnolting/neorv32-riscof
✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
ghdl isa neorv32 processor risc-v riscof riscv sail-riscv verification vhdl
Last synced: 09 Nov 2024
https://github.com/sifive/ProcKami
Kami based processor implementations and specifications
coq formal-verification hardware hardware-designs riscv riscv-simulator
Last synced: 09 Nov 2024
https://github.com/rinhizakura/riscv-emulator
A project for learning RISC-V architecture purpose
c emulator riscv riscv-emulator
Last synced: 07 Nov 2024
https://github.com/sifive/prockami
Kami based processor implementations and specifications
coq formal-verification hardware hardware-designs riscv riscv-simulator
Last synced: 10 Nov 2024
https://github.com/jiegec/rvv-kernels
Implements kernels with RISC-V Vector
Last synced: 09 Nov 2024
https://github.com/swetland/os-workshop
Some materials and sample source for RV32 OS projects.
Last synced: 16 Nov 2024
https://github.com/h1romas4/m5stamp-c3dev
This is a development board for the M5Stamp C3 (RISC-V/FreeRTOS).
arduino arduino-esp32 assemblyscript esp32 esp32c3 jtag m5stack m5stamp risc-v riscv wasm3 webassembly
Last synced: 10 Oct 2024
https://github.com/rcore-os/riscv-sbi-rt
A mininal runtime / startup for Supervisor Binary Interface (SBI) on RISC-V.
Last synced: 14 Nov 2024
https://github.com/socxin/risc-v
RISC-V Architecture
architecture qitas risc-v riscv
Last synced: 22 Dec 2024
https://github.com/ariya/hello-c90
Hello world in C90 (ANSI C) built for Intel/AMD, PowerPC, System z, ARM, MIPS, RISC-V
amd ansi-c arm c c90 clang continous-integration digital-mars gcc intel mips multi-platform powerpc ppc64 ppc64le risc-v riscv tcc visual-studio
Last synced: 09 Nov 2024
https://github.com/losfair/magicore
An out-of-order processor that supports multiple instruction sets.
Last synced: 14 Oct 2024
https://github.com/michaeljclark/musl-riscv-toolchain
riscv-linux musl gcc toolchain bootstrap scripts
gcc musl musl-libc musl-riscv-toolchain risc-v riscv toolchain
Last synced: 05 Nov 2024
https://github.com/celebi-pkg/riscv-assembler
RISC-V Assembly code assembler package for Python.
assembler assembly instruction-set-architecture python risc-v riscv riscv-assembler
Last synced: 14 Oct 2024
https://github.com/dramforever/fiveth
A stack-based language implemented in RISC-V assembly
Last synced: 18 Nov 2024
https://github.com/jn513/risco-5
Multi-cycle RISC-V processor with RV32I/E[M] implementation, built during a few days off.
arquitetura fpga risc-v riscv riscv32 verilog verilog-hdl
Last synced: 15 Dec 2024
https://github.com/eigenraven/rvasm
RISC-V Assembler
assembler extensible risc-v riscv rust
Last synced: 09 Nov 2024
https://github.com/ccelio/riscv-hpmcounters
A simple utility for doing RISC-V HPM perf monitoring.
Last synced: 27 Oct 2024
https://github.com/0x5457/riscv-emulator
🖥️ a toy riscv emulator, written in Rust
Last synced: 07 Nov 2024
https://github.com/lichtso/riscv-llvm-templates
Code templates to get started experimenting with the RISC-V LLVM toolchain
code-templates llvm risc-v riscv
Last synced: 07 Nov 2024
https://github.com/mikeroyal/assembly-guide
Assembly Guide
arm-assembly arm-assembly-language assembly assembly-language assembly-language-programming assembly-x86 assembly-x86-64 awesome awesome-list awesome-readme intel risc-v riscv x86 x86-64
Last synced: 03 Oct 2024
https://github.com/lupyuen/bl602-simulator
BL602 / BL604 Simulator in WebAssembly
bl602 embedded riscv rust webassembly
Last synced: 14 Nov 2024
https://github.com/new-tee-os/new-tee-os
A brand new OS that runs in various kinds of TEEs and supports Linux ABI
keystone-enclave riscv rust-os sgx-enclave
Last synced: 11 Nov 2024
https://github.com/mytechnotalent/hacking-risc-v
A FREE comprehensive step-by-step embedded RISC-V hacking tutorial covering RISC-V Embedded Software Development to Reverse Engineering.
arduino assembler assembly-language hack hacking platformio reverse-engineering risc-v riscv
Last synced: 10 Oct 2024
https://github.com/andelf/longan-nano-playground-rs
Longan Nano board(GD32VF103) examples, in Rust, under macOS. Bad Apple included.
longan-nano riscv rust-embedded
Last synced: 20 Oct 2024
https://github.com/nuclei-software/platform-nuclei
Nuclei: development platform for PlatformIO
build-system embedded-systems nuclei nuclei-sdk platformio platformio-platform risc-v riscv
Last synced: 01 Dec 2024
https://github.com/platformio/platform-sifive
SiFive: development platform for PlatformIO
platformio platformio-platform risc-v riscv sifive
Last synced: 07 Oct 2024
https://github.com/risto97/peakrdl-halcpp
C++ 17 Hardware abstraction layer generator from systemrdl
cpp cpp17 cpu embedded processor programming risc-v riscv systemonchip systemrdl systemrdl-compiler
Last synced: 14 Dec 2024
https://github.com/cla7aye15i4nd/trivial-riscv-cpu
A trivial riscv cpu with tomasulo algorithm implemented in Verilog HDL. Support out-of-order execution and pipline and can run in FPGA with at 100MHz.
computer-architecture fpga pipeline riscv tomasulo-algorithm verilog-hdl
Last synced: 18 Nov 2024
https://github.com/donn/oak.js
Online RISC-V/MIPS Assembler & Simulator
instruction-set-simulator iss risc-v riscv
Last synced: 28 Nov 2024
https://github.com/stupremee/spear
RISC-V emulator that is focused on correctness and tries to support as many features as possible.
emulator riscv riscv-emulator riscv-simulator rust
Last synced: 14 Oct 2024
https://github.com/calint/tang-nano-9k--riscv--cache-psram
RISC-V implementation of rv32i for FPGA board Tang Nano 9K utilizing on-board burst PSRAM and flash
fpga riscv rv32i systemverilog tang-nano tang-nano-9k
Last synced: 11 Nov 2024
https://github.com/rustsbi/sbi-spec
Definitions and constants in RISC-V Supervisor Binary Interface (RISC-V SBI)
Last synced: 11 Nov 2024
https://github.com/hexdae/toolchains_riscv_gnu
RISC-V bazel toolchains for GCC compilation
bare-metal bazel gcc riscv toolchain
Last synced: 23 Nov 2024
