https://github.com/shpegun60/open_std_fpga

This std libraries on fpga

fpga-std standard-library-fpga verilog

Last synced: 18 Jan 2025

https://github.com/qasimwani/karnaugh-map-batch-calculator

Calculates Multiple Karnaugh Maps at once using Selenium and custom built parser. The program then converts the Boolean Expressions into Dataflow Verilog (VHDL)

converts dataflow-verilog karnaugh-map karnaugh-map-solver karnaugh-maps selenium verilog web-scraping

Last synced: 27 Dec 2024

https://github.com/markmll/todaystart-a153

As-shipped demo for the Altera Cyclone TodayStart-A153 board. Requires Quartus-II 10.1 SP1 minimum.

fpga verilog vhdl

Last synced: 21 Dec 2024

https://github.com/risto97/socmake

Build system for RTL and SoC designs

cmake cpu hardware rtl simulation systemc systemonchip systemrdl verilog

Last synced: 21 Dec 2024

https://github.com/kenny2github/verilog-cpu

A very rudimentary and haphazard CPU created in Verilog.

cpu verilog verilog-hdl

Last synced: 20 Dec 2024

https://github.com/ethanuppal/berkeley-hardfloat

Downstream hardfloat with custom patches

berkeley floating-point verilog

Last synced: 07 Feb 2025

https://github.com/rinminase/cpe512

verilog

Last synced: 27 Dec 2024

https://github.com/a-bdellatif/digitaldesignwithverilog

Simple circuits designed with verilog

asic behavioural dataflow design digitalsystems fpga structural verilog verilog-code verilog-project verilogprojects

Last synced: 03 Feb 2025

https://github.com/ted-xie/icesuite

One-stop-shop for all the tools you need to get started with the iCE40 breakout board.

fpga ice40 lattice verilog yosys

Last synced: 12 Jan 2025

https://github.com/toruniina/brainfxck-circuit

run brainfxck on FPGA

brainfuck verilog

Last synced: 03 Feb 2025

https://github.com/cepdnaclk/e18-co502-rv32im-pipeline-implementation-group03

RV32IM Pipeline Processor

risc-v verilog

Last synced: 11 Jan 2025

https://github.com/prinuvinod/digital-lab

These are some Verilog Programs

digital verilog

Last synced: 06 Jan 2025

https://github.com/ain1084/machxo2_serial_to_spdif_transmitter

Serial (LPCM) to S/PDIF transmitter. Using MachXO2 (1200HC QFN32).

audio machxo2 spdif verilog

Last synced: 20 Dec 2024

https://github.com/elifgokpinar/microprocessor-design

Quartus Project

microprocessor quartus verilog

Last synced: 13 Jan 2025

https://github.com/mattjesc/energy-efficient-spi-sensor-network

Energy Efficient SPI (Serial Peripheral Interface) Sensor Network

fpga spi verilog vivado

Last synced: 18 Jan 2025

https://github.com/ain1084/audio_level_meter

This is an audio level meter implemented using Verilog HDL.

audio machxo2 verilog visualization

Last synced: 20 Dec 2024

https://github.com/mattjesc/biomimetic-filtering-pwm-signal-smoothing

Biomimetic Filtering for PWM Signal Smoothing

asic biomimetics fpga pwm systemverilog verilog vhdl vivado vlsi

Last synced: 18 Jan 2025

https://github.com/kaushalmodi/nim-svvpi

Wrapper for SystemVerilog VPI headers sv_vpi_user.h and vpi_user.h

1364-2005 1800-2017 nim pli systemverilog verilog vpi

Last synced: 16 Jan 2025

https://github.com/mssola/hdl

Playing around with Hardware Description Languages.

hdl systemverilog verilog

Last synced: 27 Jan 2025

https://github.com/mcleber/verilog_half_adder

Verilog half adder

half-adder verilog verilog-hdl

Last synced: 12 Jan 2025

https://github.com/panxuc/xucpu

NSCSCC “龙芯杯” 2024 个人赛 LoongArch 赛道参赛作品

fpga loongarch nscscc verilog

Last synced: 01 Feb 2025

https://github.com/niqzart/pylohd

High-level framework for simplification and systematization of processes in electronic design

converter hdl python thesis-project verilog

Last synced: 01 Feb 2025

https://github.com/cepdnaclk/e18-co502-rv32im-pipeline-implementation-group4

Single-cycle MIPS-like processor with a memory subsystem including a cache.

computer-architecture risc-v verilog

Last synced: 11 Jan 2025

https://github.com/seyed0123/vendor

A vending machine system

verilog

Last synced: 24 Jan 2025

https://github.com/rejunity/atari-2600-fpga

Continue development of Atari 2600 in Verilog. Based on the original work by Daniel Beer.

atari-2600 atari2600 fpga retrogaming verilog

Last synced: 24 Jan 2025

https://github.com/assem-elqersh/mips-processor-designs

Comprehensive repository containing Verilog implementations of MIPS processors. Includes both single-cycle and multi-cycle architectures, each in separate directories, with full simulation testbenches and modular design components for educational and development purposes.

computer-architecture educational hardware-designs mips mips-architecture processor-design simulation verilog

Last synced: 27 Jan 2025

https://github.com/orcalinux/computer-organization-and-architecture

Verilog code examples and materials for Computer Organization.

8086-microprocessor computer-architecture computer-organization modelsim pic programmable-interrupt-controller qu synthesis-project verilog

Last synced: 20 Dec 2024

https://github.com/anthonyhuang19/fpga-embedded-systems

This project focuses on designing digital circuits and microprocessors using FPGA, covering topics like Boolean logic, combinational circuits, state machines, CPU design, and memory structures (ROM/RAM).

fpga stata verilog

Last synced: 19 Jan 2025

https://github.com/lovc21/vhdl-code-from-lab

This repository includes VHDL code for laboratory projects conducted in an Integrated Circuits and Design course. It particularly emphasizes the 'Generator Tonov Jakob' project, which has been enhanced to showcase varying frequencies and tones. For detailed insights into these projects, refer to the course website.

verilog vhdl vhdl-code

Last synced: 19 Jan 2025

https://github.com/mc256/eecs2021

DO NOT COPY. MAKE SURE U UNDERSTAND.

eecs2021 mips verilog yorkuniversity

Last synced: 24 Jan 2025

https://github.com/soham9284/smart-home-automation-system

The Smart Home Automation System is a comprehensive solution that integrates sensors, manual controls, and automated logic to manage lighting, temperature, security, and emergency responses efficiently.

fpga fpga-board verilog xilinx-vivado

Last synced: 02 Feb 2025

https://github.com/memgonzales/hdl-flip-flop

Compilation of Verilog behavioral models and test benches for the four types of flip-flops (SR, JK, D, and T)

behavioral-modeling computer-architecture flip-flop sequential-circuits verilog

Last synced: 20 Jan 2025

https://github.com/yasnakateb/threshold

🖼✏️ My first baby steps into the world of image processing

grayscale image-processing threshold verilog verilog-hdl xilinx-ise

Last synced: 20 Jan 2025

https://github.com/sofiavalos/verilog_ethernet_10g_mac

Bloques y bancos de pruebas MAC para Ethernet 10G.

ethernet mac verilog

Last synced: 06 Feb 2025

https://github.com/saifalomari99/fpga_projects_saifalomari

This Repository is to showcase Saif Alomari's FPGA projects. Includes 25 high-level FPGA projects in various HDLs.

fpga systemverilog verilog

Last synced: 28 Dec 2024

https://github.com/mtaciano/fpgmips

Um processador baseado na arquitetura MIPS 32bits no FPGA DE2-115.

fpga mips processor verilog

Last synced: 06 Feb 2025

https://github.com/niw/chisel_test

A simple Chisel test project for myself to learn Chisel and FPGA.

chisel3 fpga orangecrab scala tinyfpga verilog

Last synced: 06 Jan 2025

https://github.com/davoodeh/verilog2hspice

Do some simple conversions on Verilog files to make them compatible with HSpice

converter hdl hspice verilog

Last synced: 08 Feb 2025

https://github.com/shuregg/fpga-practicum

learning about FPGA

fpga fpga-programming rtl systemverilog verilog vivado xilinx

Last synced: 06 Feb 2025

https://github.com/shuregg/miet-interfaces

Interfaces of computing systems

interfaces protocols verilog verilog-hdl

Last synced: 06 Feb 2025

https://github.com/dpieve/university

A resource for students learning programming and personal reference.

assembly cpp haskell haskell-exercises java matlab prolog python shell unifei-university verilog

Last synced: 22 Dec 2024

https://github.com/chaseruskin/setup-orbit

GitHub Action to install Orbit

action continuous-integration hdl systemverilog utilities verilog vhdl

Last synced: 26 Jan 2025

https://github.com/javiidiazglez/ec

Estructuras de Computadores

verilog

Last synced: 01 Jan 2025

https://github.com/kulp/tappy

tappy is a tiny Verilog driver for PS/2 keyboards, for use in FPGAs

fpga verilog

Last synced: 16 Dec 2024

https://github.com/yasnakateb/blinky

💡A Quartus II project testing the functionality of the Altera Cyclone IV EP4CE6E22C8N board

altera-fpga fpga verilog verilog-hdl

Last synced: 20 Jan 2025

https://github.com/aliiiw/computer-architecture-lab

Implement Mips cpu with Verilog

forwarding mips pipeline verilog

Last synced: 30 Jan 2025

https://github.com/et312/custom_cpu

Custom 16-bit RISC-based CPU with custom control unit, ALU, and memory block designs

fpga verilog

Last synced: 16 Dec 2024

https://github.com/abstractmachines/verilog-shift-register

A shift register in Verilog. Bidirectional pin use.

embedded-systems hardware shift-register verilog

Last synced: 06 Feb 2025

https://github.com/centuriontheman/efficientmodulooperations

The project implements a high-performance modulo algorithm.

modulo modulo-arithmetics python university university-project verilog

Last synced: 05 Feb 2025

https://github.com/mark-mdo47/fpga_rbg_2_rbgw

Lattice iCE40 FPGA convert WS2812b RGB from ESP32 to SK6812 RGBW

apio esp32-arduino fpga ice40 icestick led sk6812 verilog ws2812b

Last synced: 22 Jan 2025

https://github.com/tdholmes/digitaldesign-pong

Verilog Pong game designed for Digital Design in December of 2013.

pong verilog

Last synced: 29 Jan 2025

https://github.com/arsham-lh/logic-circuits

Simulation of logic circuits using Verilog, Proteus and other tools.

digital-circuits fsm logic-circuits mealy-machine moore-machine proteus verilog

Last synced: 17 Jan 2025

https://github.com/arsham-lh/computer-architecture

Code files related to the Computer Architecture course, taught by M. Movahedin

computer-architecture mips-assembly multi-cycle-processor single-cycle-processor verilog

Last synced: 17 Jan 2025

https://github.com/abshar-shihab/the-fast-matrix-multiplication-on-fpga

This repository explores efficient matrix multiplication on FPGA hardware. Communication between the PC and FPGA is implemented through UART.

fpga nexus-3 pipelined uart verilog

Last synced: 23 Dec 2024

https://github.com/gcerpa01/compe470

Work of my projects I worked on while enrolled in SDSU's COMPE470 Digital Circuits course in Spring 2023

verilog verilog-hdl vivado

Last synced: 17 Jan 2025

https://github.com/madh93/scpu

Simple 16-bit CPU written in Verilog.

cpu datapath verilog

Last synced: 29 Jan 2025

https://github.com/28ritu/alu

An ALU Design in Verilog

alu verilog waveform

Last synced: 22 Dec 2024

https://github.com/paulchen2713/introduction_to_veriloghdl

Digital System Design Course Practices

verilog

Last synced: 23 Jan 2025

https://github.com/cr0a3/hardwarelib

A libary to create asics in short time

asic hardware verilog

Last synced: 23 Jan 2025

https://github.com/polaris000/cs_f342

Lab assignments and some practise done for the Computer Architecture course at BITS Pilani

assembly bits-pilani comparch computer-architecture labs practise verilog

Last synced: 09 Jan 2025

https://github.com/jackson-nestelroad/verilog-mips-processor

Single-cycle 32-bit MIPS processor implemented in SystemVerilog.

cpu mips processor verilog

Last synced: 29 Jan 2025

https://github.com/andrejchoo/cpldctrum

ZX Spectrum clone on CPLD

cpld divmmc verilog zx-spectrum

Last synced: 05 Feb 2025

https://github.com/j-m-li/logical16x16

Hardware Description Language for EPROM and FLASH memories

eprom public-domain verilog

Last synced: 18 Nov 2024

https://github.com/susiejojo/sobel_filter

Sobel filter for edge detection in images supporting parallel processing using Verilog on Xilinx ISE 13.4

hdl sobel-filter verilog xilinx-ise

Last synced: 17 Dec 2024

https://github.com/fuwn/iverilog-test-bench

☀️ Icarus Verilog Test-bench Template

de10 icarus-verilog verilog

Last synced: 05 Feb 2025

https://github.com/mongshil553/digital-engineering-verilog-assignments

Sophomore 2021 1st Semester Digital Engineering Verilog Assignments

fpga-programming verilog xilinx-vivado

Last synced: 13 Jan 2025

https://github.com/tanuj-maheshwari/fpga

Configurable FPGA Fabric simulated in Verilog

fpga verilog

Last synced: 23 Jan 2025

https://github.com/caite21/cpu-core

16-bit CPU Core Design in Verilog

cpu verilog xilinx-vivado

Last synced: 22 Jan 2025

https://github.com/wassimhedfi/fpga_adc_pwm_motorcontrol

This repository contains the implementation of a motor speed control system using an FPGA. The speed is adjusted dynamically through a potentiometer, leveraging ADC for analog-to-digital conversion and PWM for precise motor control.

adc de10-lite fpga html motor-speed pwm verilog vhdl

Last synced: 31 Jan 2025

https://github.com/mthszr/stopwatch-verilog

Projeto da 2ª unidade, para a disciplina de Sistemas Digitais, no qual consiste em desenvolver um Cronômetro Digital, utilizando Verilog com a base de Máquina de Estados Finitos.

verilog verilog-hdl

Last synced: 22 Jan 2025

https://github.com/pseudoincorrect/verilog_labs

Verilog labs

c dsp soft-cpu verilog

Last synced: 16 Dec 2024

https://github.com/akielaries/hwverif

Sandbox for exploring Hardware Verification

verilog

Last synced: 20 Jan 2025

https://github.com/jjateen/snake-game-verilog

This repository showcases a Verilog-based Snake and Apple Game, developed for the ECL 106: Digital System Design with HDL course. Running on an Altera DE10-Lite FPGA board and displayed on a VGA monitor, players control a snake to collect apples while avoiding obstacles. The snake grows longer with each apple, making the game progressively harder.

altera-fpga de10-lite fpga quartus-prime verilog verilog-project

Last synced: 17 Jan 2025

https://github.com/seojuncha/fromthetransistor-fork

geohot's fromthetransistor project with a little modification.

assembler assembly c compiler fromthetransistor python uart verilog

Last synced: 05 Feb 2025

https://github.com/theoplayz2/eda-explorer

Инструмент на Python для разведочного анализа данных (EDA) и визуализации, поддерживающий загрузку данных CSV и JSON, с модульной архитектурой ООП. Практическая работа по теме: "Обнаружение и визуализация данных для понимания их сущности" дисциплины "МДК 13.01: Основы применения методов искусственного интеллекта в программировании".

analysis battery-life cqrs csharp data-analysis eeg-analysis exploratorydataanalysis json-visualization matplotlib messaging profile-report python verilog visualization

Last synced: 28 Jan 2025