https://github.com/shiro-raven/verilog-mips

A verilog-based MIPS processor with pipelining

assembly mips mips-architecture verilog

Last synced: 01 Feb 2025

https://github.com/clementkim/logic-circuit-verilog

아주대학교 논리회로 - Verilog를 이용한 프로젝트 코드

logic-circuit verilog

Last synced: 15 Dec 2024

https://github.com/tdjsnelling/garbled-circuits

Yao’s Garbled Circuits in TypeScript

cryptography garbled-circuits javascript mpc multiparty-computation nodejs oblivious-transfer typescript verilog

Last synced: 15 Dec 2024

https://github.com/centuriontheman/efficientmodulooperations

The project implements a high-performance modulo algorithm.

modulo modulo-arithmetics python university university-project verilog

Last synced: 05 Feb 2025

https://github.com/ethanuppal/berkeley-hardfloat

Downstream hardfloat with custom patches

berkeley floating-point verilog

Last synced: 07 Feb 2025

https://github.com/jminjares4/digital-system-2

Digital System 2 Lab

digital-design verilog

Last synced: 10 Jan 2025

https://github.com/abstractmachines/verilog-shift-register

A shift register in Verilog. Bidirectional pin use.

embedded-systems hardware shift-register verilog

Last synced: 06 Feb 2025

https://github.com/aliiiw/computer-architecture-lab

Implement Mips cpu with Verilog

forwarding mips pipeline verilog

Last synced: 30 Jan 2025

https://github.com/chaseruskin/setup-orbit

GitHub Action to install Orbit

action continuous-integration hdl systemverilog utilities verilog vhdl

Last synced: 26 Jan 2025

https://github.com/rinminase/cpe512

verilog

Last synced: 27 Dec 2024

https://github.com/a-bdellatif/digitaldesignwithverilog

Simple circuits designed with verilog

asic behavioural dataflow design digitalsystems fpga structural verilog verilog-code verilog-project verilogprojects

Last synced: 03 Feb 2025

https://github.com/dpieve/university

A resource for students learning programming and personal reference.

assembly cpp haskell haskell-exercises java matlab prolog python shell unifei-university verilog

Last synced: 22 Dec 2024

https://github.com/mtaciano/fpgmips

Um processador baseado na arquitetura MIPS 32bits no FPGA DE2-115.

fpga mips processor verilog

Last synced: 06 Feb 2025

https://github.com/toruniina/brainfxck-circuit

run brainfxck on FPGA

brainfuck verilog

Last synced: 03 Feb 2025

https://github.com/cepdnaclk/e18-co502-rv32im-pipeline-implementation-group03

RV32IM Pipeline Processor

risc-v verilog

Last synced: 11 Jan 2025

https://github.com/prinuvinod/digital-lab

These are some Verilog Programs

digital verilog

Last synced: 06 Jan 2025

https://github.com/mosure/ece552-project-fall-2018

ece552 uw-madison verilog

Last synced: 27 Jan 2025

https://github.com/mohammadmahdi-abdolhosseini/computer-architecture-lab

Computer Architecture Lab - Assignments - Fall 2023

arm-processor fpga modelsim quartus2 systemverilog verilog vhdl

Last synced: 07 Jan 2025

https://github.com/yappy2000d/fpga-make-win

Use the make tool to automate your work in CLI.

makefile quartus verilog

Last synced: 25 Jan 2025

https://github.com/shuregg/fpga-practicum

learning about FPGA

fpga fpga-programming rtl systemverilog verilog vivado xilinx

Last synced: 06 Feb 2025

https://github.com/shuregg/miet-interfaces

Interfaces of computing systems

interfaces protocols verilog verilog-hdl

Last synced: 06 Feb 2025

https://github.com/kulp/tappy

tappy is a tiny Verilog driver for PS/2 keyboards, for use in FPGAs

fpga verilog

Last synced: 16 Dec 2024

https://github.com/ain1084/machxo2_serial_to_spdif_transmitter

Serial (LPCM) to S/PDIF transmitter. Using MachXO2 (1200HC QFN32).

audio machxo2 spdif verilog

Last synced: 20 Dec 2024

https://github.com/et312/custom_cpu

Custom 16-bit RISC-based CPU with custom control unit, ALU, and memory block designs

fpga verilog

Last synced: 16 Dec 2024

https://github.com/princeranjan03/imageencryption_i-chip

This project focuses on creating a hardware-based encryption and decryption system that implements the Data Encryption Standard (DES) algorithm.

cipher cryptography data-encryption data-encryption-standard encoding encryption-decryption fpga image image-processing opencv rtldesign source-coding verilog verilog-hdl verilog-project vivado xilinx xilinx-vivado

Last synced: 31 Jan 2025

https://github.com/j-m-li/3o3

Ternary CPU for EPROM and FLASH memories

eprom public-domain verilog

Last synced: 01 Feb 2025

https://github.com/davoodeh/verilog2hspice

Do some simple conversions on Verilog files to make them compatible with HSpice

converter hdl hspice verilog

Last synced: 08 Feb 2025

https://github.com/ain1084/audio_level_meter

This is an audio level meter implemented using Verilog HDL.

audio machxo2 verilog visualization

Last synced: 20 Dec 2024

https://github.com/1sand0s/ssp-master-and-slave-verilog-module

FSM based SPI/SSP Master and Slave Verilog Module

fifo-buffer rtl verilog verilog-hdl

Last synced: 08 Feb 2025

https://github.com/abshar-shihab/the-fast-matrix-multiplication-on-fpga

This repository explores efficient matrix multiplication on FPGA hardware. Communication between the PC and FPGA is implemented through UART.

fpga nexus-3 pipelined uart verilog

Last synced: 23 Dec 2024

https://github.com/cepdnaclk/e18-co502-rv32im-pipeline-implementation-group4

Single-cycle MIPS-like processor with a memory subsystem including a cache.

computer-architecture risc-v verilog

Last synced: 11 Jan 2025

https://github.com/assem-elqersh/mips-processor-designs

Comprehensive repository containing Verilog implementations of MIPS processors. Includes both single-cycle and multi-cycle architectures, each in separate directories, with full simulation testbenches and modular design components for educational and development purposes.

computer-architecture educational hardware-designs mips mips-architecture processor-design simulation verilog

Last synced: 27 Jan 2025

https://github.com/akielaries/hwverif

Sandbox for exploring Hardware Verification

verilog

Last synced: 20 Jan 2025

https://github.com/roscibely/arithmetic-logic-unit

A simple arithmetic logic unit (ALU) with System verilog

alu arithmetic verilog vhdl

Last synced: 21 Jan 2025

https://github.com/sea-n/nctu-108b-dcd

108 Spring - Digital Circuit Design

homework nctu verilog

Last synced: 07 Jan 2025

https://github.com/orcalinux/computer-organization-and-architecture

Verilog code examples and materials for Computer Organization.

8086-microprocessor computer-architecture computer-organization modelsim pic programmable-interrupt-controller qu synthesis-project verilog

Last synced: 20 Dec 2024

https://github.com/soham9284/smart-home-automation-system

The Smart Home Automation System is a comprehensive solution that integrates sensors, manual controls, and automated logic to manage lighting, temperature, security, and emergency responses efficiently.

fpga fpga-board verilog xilinx-vivado

Last synced: 02 Feb 2025

https://github.com/fuwn/iverilog-test-bench

☀️ Icarus Verilog Test-bench Template

de10 icarus-verilog verilog

Last synced: 05 Feb 2025

https://github.com/ranitmanik/cs-verilog-assignments

A collection of Verilog code snippets and assignments for computer science coursework.

assignment coding iverilog low-level-programming practice practice-programming verilog

Last synced: 28 Jan 2025

https://github.com/pawel2000pl/verilogleddriver

Led RGB driver written in verilog, implemented for Mimas A7 Mini FPGA Development Board

fpga led-controller led-driver pwm pwm-driver systemverilog verilog vivado

Last synced: 22 Jan 2025

https://github.com/sofiavalos/verilog_ethernet_10g_mac

Bloques y bancos de pruebas MAC para Ethernet 10G.

ethernet mac verilog

Last synced: 06 Feb 2025

https://github.com/pseudoincorrect/verilog_labs

Verilog labs

c dsp soft-cpu verilog

Last synced: 16 Dec 2024

https://github.com/seojuncha/fromthetransistor-fork

geohot's fromthetransistor project with a little modification.

assembler assembly c compiler fromthetransistor python uart verilog

Last synced: 05 Feb 2025

https://github.com/samiyaalizaidi/fpga

Verilog implementation of the basic structure of an FPGA

digital-system-design fpga verilog vivado

Last synced: 16 Jan 2025

https://github.com/saifalomari99/fpga_projects_saifalomari

This Repository is to showcase Saif Alomari's FPGA projects. Includes 25 high-level FPGA projects in various HDLs.

fpga systemverilog verilog

Last synced: 28 Dec 2024

https://github.com/skpro-glitch/resume

Find my resume, encapsulating my most prominent projects and experiences relevant for an entry level Hardware Engineering role. - Soham Kapur

algorithms-and-data-structures cadence cadence-virtuoso drone electronics-engineering java java-programming ltspice matlab soham-kapur sohamkapur team-aviators-international uav verilog verilog-hdl verilog-processor vit-chennai vit-university vitc vitchennai

Last synced: 05 Feb 2025

https://github.com/jminjares4/digital-system-2-template

Digital System 2 Template

digital-design verilog

Last synced: 10 Jan 2025

https://github.com/samiyaalizaidi/pipelined-risc-v-processor

A Pipelined RISC-V Processor with forwarding support and hazard detection.

assembly computer-architecture pipelining processor processor-architecture risc-v verilog vivado

Last synced: 16 Jan 2025

https://github.com/rehankarthikchandralal/implementation-of-a-configurable-neural-processing-unit-with-input-and-weight-stationary-dataflows

Used Verilog to design an entire NPU that supports two different kinds of dataflows to enable data reuse in order to reduce power consumption and resource utilization

neural-network-hardware verilog

Last synced: 17 Dec 2024

https://github.com/niw/chisel_test

A simple Chisel test project for myself to learn Chisel and FPGA.

chisel3 fpga orangecrab scala tinyfpga verilog

Last synced: 06 Jan 2025

https://github.com/javiidiazglez/ec

Estructuras de Computadores

verilog

Last synced: 01 Jan 2025

https://github.com/justin-marian/tiny-risc-v

Minimalist RISC-V with a five-stage pipeline. It serves as a platform for understanding processor design principles.

isa-architecture risc-v-architecture verilog

Last synced: 27 Dec 2024

https://github.com/lasithaamarasinghe/uart-implementation-in-fpga

This is a group assignment done under semester 4 module EN2111:Electronic Circuit Design, .

fpga quartus-prime uart verilog

Last synced: 10 Jan 2025

https://github.com/mongshil553/digital-engineering-verilog-assignments

Sophomore 2021 1st Semester Digital Engineering Verilog Assignments

fpga-programming verilog xilinx-vivado

Last synced: 13 Jan 2025

https://github.com/miku-218525/asic_lab

verilog

Last synced: 25 Dec 2024

https://github.com/urish/tt06-spell

A minimal, stack-based programming language created for The Skull CTF

tinytapeout verilog wizardry

Last synced: 11 Jan 2025

https://github.com/mohamad-shosha/alu-verilog-proteus

This 4-bit ALU design project has been implemented as part of the [Computer Aided Design] in the university , where we applied Verilog for hardware design and Proteus for simulation.

proteus verilog

Last synced: 28 Dec 2024

https://github.com/dev-ritik/calculator

Xilinx college project

calculator college-project gui java-applet verilog xilinx

Last synced: 30 Jan 2025

https://github.com/3-o-3/cod5

Public Domain (⊄) Computer on FPGA

fpga fpga-soc public-domain ternary ternary-computer verilog

Last synced: 18 Dec 2024

https://github.com/calint/znxcr

experimental retro 16 bit cpu written in verilog xilinx vivado intended for fpga Cmod S7 from Digilent

16-bit cmod-s7 cpu fpga verilog

Last synced: 10 Jan 2025

https://github.com/calint/tang-nano-9k--riscv

RISC-V rv32i implementation on Tang Nano 9K

risc-v rv32i tang-nano-9k verilog

Last synced: 10 Jan 2025

https://github.com/shishir-dey/pcb-dev-fpga-ice40

A 2 layer development board with a Lattice Semiconductor ICE40UP5K-SG48ITR FPGA. Made with KiCad

development-board fpga hardware pcb-design verilog

Last synced: 14 Jan 2025

https://github.com/calint/riscv

experiments implementing a risc-v cpu to gain experience with verilog and minimalistic cpu design

cmod-s7 cpu fpga iverilog risc-v riscv32i verilog vivado

Last synced: 10 Jan 2025

https://github.com/rpigor/tpsim

TPSim (Timing and Power Simulator) is a gate-level circuit simulator with timing and power estimation capabilities

eda power-analysis simulator timing-analysis verilog

Last synced: 06 Jan 2025

https://github.com/idorobots/upduino-blinky

Two simple Upduino projects that blink an RGB LED in various ways.

blinky fpga ice40 ice40up5k led upduino upduino-board verilog

Last synced: 20 Dec 2024

https://github.com/aledpl5/rock-paper-scissors-circuit

Uni project about the game rock-paper-scissors

blif circuit datapath datapath-design finate-state-machine sis systemverilog verilog

Last synced: 05 Jan 2025

https://github.com/namberino/simple-uart

Simple UART implementation in FPGA

fpga uart verilog

Last synced: 20 Jan 2025

https://github.com/arefin994/bitstreamos

BitStreamOS --- A custom-designed MIPS CPU and operating system built from scratch. Features include a custom instruction set, assembler for converting assembly code to binary, CPU simulation with test benches, waveform visualization, and a basic OS implementation.

asm cpu mips-assembly os verilog

Last synced: 01 Jan 2025

https://github.com/justin-marian/fsm-vending-machine

FSM vending machine, it dispenses products based on user input and provides change based on the money introduced.

fsm vending-machine-proplem verilog

Last synced: 27 Dec 2024

https://github.com/youseftareq33/digital_buildcombinationalcircuit_1

Using Verilog HDL on Quartus application build combinational circuit

combinational-circuit verilog

Last synced: 24 Dec 2024

https://github.com/cosminpopescu14/fpga

Sisteme FPGA

fpga verilog

Last synced: 25 Dec 2024

https://github.com/ilovebacteria/elevator-state-machine

My Digital Logic course project - Elevator state machine

digital-logic moore-machine state-machine verilog

Last synced: 14 Nov 2024

https://github.com/birdybro/nand2tetris_mister

Nand2Tetris for MiSTer (as a learning experience for me).

hdl mister misterfpga tetris verilog verilog-hdl

Last synced: 01 Feb 2025

https://github.com/davidvarshanidze/cpu

CPU implementation in MIPS Assembly and Verilog

cpu mips-assembly verilog

Last synced: 04 Feb 2025

https://github.com/camilaqpereira/oficina-verilog-siecomp

Neste repositórios estão disponibilizados todos os arquivos utilizados na Oficina Introdução ao Verilog Comportamental ministrado na XXXI SIECOMP (UEFS). Além disso, estão listados múltiplos recursos para estudo da linguagem.

oficina verilog verilog-code verilog-hdl

Last synced: 23 Jan 2025