https://github.com/davoodeh/verilog2hspice

Do some simple conversions on Verilog files to make them compatible with HSpice

converter hdl hspice verilog

Last synced: 15 Dec 2024

https://github.com/dibahk/verilog-language

A collection of verilog codes

gates verilog

Last synced: 08 Jan 2025

https://github.com/xigh/tinyfpga-counter

simple 1hz tinyfpga counter

fpga tinyfpga-bx verilog

Last synced: 08 Jan 2025

https://github.com/idorobots/upduino-blinky

Two simple Upduino projects that blink an RGB LED in various ways.

blinky fpga ice40 ice40up5k led upduino upduino-board verilog

Last synced: 20 Dec 2024

https://github.com/aledpl5/rock-paper-scissors-circuit

Uni project about the game rock-paper-scissors

blif circuit datapath datapath-design finate-state-machine sis systemverilog verilog

Last synced: 05 Jan 2025

https://github.com/mohammadmahdi-abdolhosseini/computer-architecture-lab

Computer Architecture Lab - Assignments - Fall 2023

arm-processor fpga modelsim quartus2 systemverilog verilog vhdl

Last synced: 07 Jan 2025

https://github.com/mosure/ece552-project-fall-2018

ece552 uw-madison verilog

Last synced: 29 Nov 2024

https://github.com/sea-n/nctu-108b-dcd

108 Spring - Digital Circuit Design

homework nctu verilog

Last synced: 07 Jan 2025

https://github.com/rogerfan48/course-soph1-hdl

Materials and coursework for Hardware Design Lab (Sophomore Fall). Contains exercises, assignments, and laboratory work.

verilog vivado

Last synced: 08 Jan 2025

https://github.com/kassane/fpga_course

Testing conducted during verilog studies

fpga verilog

Last synced: 13 Nov 2024

https://github.com/peplxx/morse-coder

This project was made for optional fpga project during F23 Computer Architecture course. This is Quartus Project for turning fpga board into morse coder.

fpga-board fpga-programming morse-code quartus-prime verilog

Last synced: 20 Dec 2024

https://github.com/arsham-lh/computer-architecture

Code files related to the Computer Architecture course, taught by M. Movahedin

computer-architecture mips-assembly multi-cycle-processor single-cycle-processor verilog

Last synced: 16 Nov 2024

https://github.com/arsham-lh/logic-circuits

Simulation of logic circuits using Verilog, Proteus and other tools.

digital-circuits fsm logic-circuits mealy-machine moore-machine proteus verilog

Last synced: 16 Nov 2024

https://github.com/strwdr/MaximatorZXSpectrum

ZX Spectrum implementation for maximator board

board fpga hdl max10 maximator nios soc verilog zx zx-spectrum

Last synced: 24 Oct 2024

https://github.com/ranitmanik/cs-verilog-assignments

A collection of Verilog code snippets and assignments for computer science coursework.

assignment coding iverilog low-level-programming practice practice-programming verilog

Last synced: 30 Nov 2024

https://github.com/cepdnaclk/e18-co502-rv32im-pipeline-implementation-group4

Single-cycle MIPS-like processor with a memory subsystem including a cache.

computer-architecture risc-v verilog

Last synced: 12 Nov 2024

https://github.com/cepdnaclk/e18-co502-rv32im-pipeline-implementation-group03

RV32IM Pipeline Processor

risc-v verilog

Last synced: 12 Nov 2024

https://github.com/taffarel55/verilog

Documentação dos exemplos que fiz enquanto estudava a linguagem de descrição de hardware Verilog.

verilog verilog-examples verilog-hdl

Last synced: 09 Jan 2025

https://github.com/davidf1000/sistemdigital_vhdl

Final Project for Digital System Lab. Flappy Bird Imitation Game created using VHDL for FPGA DE1.

fpga quartus verilog vhdl

Last synced: 12 Nov 2024

https://github.com/urish/tt06-spell

A minimal, stack-based programming language created for The Skull CTF

tinytapeout verilog wizardry

Last synced: 12 Nov 2024

https://github.com/tanmayv25/microprocessor-system-design

Contains the lab work of Microprocessor System Design. All the FPGA prototyping, Drivers and OS modules.

fpga-soc linux-kernel-module sensor-devices verilog xilinx-vivado

Last synced: 30 Dec 2024

https://github.com/jminjares4/digital-system-2

Digital System 2 Lab

digital-design verilog

Last synced: 11 Nov 2024

https://github.com/jminjares4/digital-system-2-template

Digital System 2 Template

digital-design verilog

Last synced: 11 Nov 2024

https://github.com/adolbyb/vhdl-fpga-nexys-a7

A collection of code from CDA 4240C: Design of Digital System and Lab

artix-7 fpga hardware-description-language hdl nexys-a7 verilog vhdl xilinx-vivado

Last synced: 19 Nov 2024

https://github.com/qasimwani/karnaugh-map-batch-calculator

Calculates Multiple Karnaugh Maps at once using Selenium and custom built parser. The program then converts the Boolean Expressions into Dataflow Verilog (VHDL)

converts dataflow-verilog karnaugh-map karnaugh-map-solver karnaugh-maps selenium verilog web-scraping

Last synced: 27 Dec 2024

https://github.com/ilovebacteria/elevator-state-machine

My Digital Logic course project - Elevator state machine

digital-logic moore-machine state-machine verilog

Last synced: 14 Nov 2024

https://github.com/shishir-dey/pcb-dev-fpga-ice40

A 2 layer development board with a Lattice Semiconductor ICE40UP5K-SG48ITR FPGA

development-board fpga hardware pcb-design verilog

Last synced: 14 Nov 2024

https://github.com/mcleber/verilog_half_adder

Verilog half adder

half-adder verilog verilog-hdl

Last synced: 13 Nov 2024

https://github.com/grachale/microarchitecture_risc-v_isa

Design of a Processor Microarchitecture Supporting a Chosen Subset of RISC-V ISA Instructions.

assembly isa microarchitecture risc-v verilog

Last synced: 13 Nov 2024

https://github.com/jjateen/snake-game-verilog

This repository showcases a Verilog-based Snake and Apple Game, developed for the ECL 106: Digital System Design with HDL course. Running on an Altera DE10-Lite FPGA board and displayed on a VGA monitor, players control a snake to collect apples while avoiding obstacles. The snake grows longer with each apple, making the game progressively harder.

altera-fpga de10-lite fpga quartus-prime verilog verilog-project

Last synced: 16 Nov 2024

https://github.com/seyed0123/vendor

A vending machine system

verilog

Last synced: 24 Nov 2024

https://github.com/coldnew/nand2tetris

My notes and impement on Nand2Tetris courses

coursearea nand2tetris personal-notes verilator verilog

Last synced: 15 Nov 2024

https://github.com/daulpavid/verilog_template

Boilerplate project template for verilog that includes directories for simulation, documentation, and formal verification.

cmake verilator verilog verilog-template

Last synced: 15 Nov 2024

https://github.com/rejunity/atari-2600-fpga

Continue development of Atari 2600 in Verilog. Based on the original work by Daniel Beer.

atari-2600 atari2600 fpga retrogaming verilog

Last synced: 24 Nov 2024

https://github.com/yasnakateb/sdramcontroller

🛠 A SDRAM controller in Verilog HDL

icarus-verilog iverilog memory-controller sdram sdram-controller verilog verilog-hdl

Last synced: 19 Nov 2024

https://github.com/kayejd/nexysa7-fpga-programming

Embedded Programming Projects

embedded-systems fpga-programming verilog vivado

Last synced: 17 Nov 2024

https://github.com/kayejd/hvac-system

School Related Project

capstone digital digital-signal-processing engineering-design verilog

Last synced: 17 Nov 2024

https://github.com/sunzey/cpu_project

recording codes of CPU under mips ISA in lecture of computer organization

buaa buaa-co cpu learning verilog

Last synced: 15 Nov 2024

https://github.com/kaleid-liner/fpga-tetris

Tetris based on Nexys4 DDR FPGA Board

fpga tetris verilog

Last synced: 15 Nov 2024

https://github.com/mc256/eecs2021

DO NOT COPY. MAKE SURE U UNDERSTAND.

eecs2021 mips verilog yorkuniversity

Last synced: 24 Nov 2024

https://github.com/yasnakateb/threshold

🖼✏️ My first baby steps into the world of image processing

grayscale image-processing threshold verilog verilog-hdl xilinx-ise

Last synced: 19 Nov 2024

https://github.com/yasnakateb/uartcommunication

☎️ UART Communication Implementation in Verilog HDL

icarus-verilog iverilog serial-communication uart uart-interface uart-protocol uart-verilog verilog

Last synced: 19 Nov 2024

https://github.com/yasnakateb/blinky

💡A Quartus II project testing the functionality of the Altera Cyclone IV EP4CE6E22C8N board

altera-fpga fpga verilog verilog-hdl

Last synced: 19 Nov 2024

https://github.com/mattjesc/biomimetic-filtering-pwm-signal-smoothing

Biomimetic Filtering for PWM Signal Smoothing

asic biomimetics fpga pwm systemverilog verilog vhdl vivado vlsi

Last synced: 17 Nov 2024

https://github.com/yasnakateb/aes

🔐 Hardware Implementation Of AES Algorithm in Verilog HDL

aes aes-128 aes-encryption encryption encryption-algorithm icarus-verilog iverilog verilog verilog-hdl

Last synced: 19 Nov 2024

https://github.com/shpegun60/open_std_fpga

This std libraries on fpga

fpga-std standard-library-fpga verilog

Last synced: 17 Nov 2024

https://github.com/susiejojo/sobel_filter

Sobel filter for edge detection in images supporting parallel processing using Verilog on Xilinx ISE 13.4

hdl sobel-filter verilog xilinx-ise

Last synced: 17 Dec 2024

https://github.com/j-m-li/logical16x16

Hardware Description Language for EPROM and FLASH memories

eprom public-domain verilog

Last synced: 18 Nov 2024

https://github.com/polaris000/cs_f342

Lab assignments and some practise done for the Computer Architecture course at BITS Pilani

assembly bits-pilani comparch computer-architecture labs practise verilog

Last synced: 09 Jan 2025

https://github.com/rosscomputerguy/slimproc

SlimProc is a 32-bit RISC instruction set

cpu-emulator fpga processor verilog

Last synced: 18 Nov 2024

https://github.com/28ritu/alu

An ALU Design in Verilog

alu verilog waveform

Last synced: 22 Dec 2024

https://github.com/azazhassankhan/verilogutilitysuite

VerilogUtilitySuite 🚀 Welcome to our SystemVerilog playground! 🤖 Dive into the world of hardware description language (HDL) with our repository, where RTL designs meet creativity.

circuit component-architecture systemverilog verilog

Last synced: 21 Nov 2024

https://github.com/madh93/scpu

Simple 16-bit CPU written in Verilog.

cpu datapath verilog

Last synced: 01 Dec 2024

https://github.com/mthszr/stopwatch-verilog

Projeto da 2ª unidade, para a disciplina de Sistemas Digitais, no qual consiste em desenvolver um Cronômetro Digital, utilizando Verilog com a base de Máquina de Estados Finitos.

verilog verilog-hdl

Last synced: 22 Nov 2024

https://github.com/caite21/cpu-core

8-bit CPU Core Design in Verilog

cpu verilog xilinx-vivado

Last synced: 22 Nov 2024

https://github.com/lsx-s-software/tiny-riscv-cpu

An implementation of RV32I ISA, including a single-cycle version and a pipelined version.

cpu pipeline risc-v verilog

Last synced: 22 Nov 2024

https://github.com/mark-mdo47/fpga_rbg_2_rbgw

Lattice iCE40 FPGA convert WS2812b RGB from ESP32 to SK6812 RGBW

apio esp32-arduino fpga ice40 icestick led sk6812 verilog ws2812b

Last synced: 22 Nov 2024

https://github.com/tanuj-maheshwari/fpga

Configurable FPGA Fabric simulated in Verilog

fpga verilog

Last synced: 22 Nov 2024

https://github.com/kaushalmodi/nim-svvpi

Wrapper for SystemVerilog VPI headers sv_vpi_user.h and vpi_user.h

1364-2005 1800-2017 nim pli systemverilog verilog vpi

Last synced: 15 Nov 2024

https://github.com/cr0a3/hardwarelib

A libary to create asics in short time

asic hardware verilog

Last synced: 22 Nov 2024

https://github.com/clementkim/logic-circuit-verilog

아주대학교 논리회로 - Verilog를 이용한 프로젝트 코드

logic-circuit verilog

Last synced: 15 Dec 2024

https://github.com/tdjsnelling/garbled-circuits

Yao’s Garbled Circuits in TypeScript

cryptography garbled-circuits javascript mpc multiparty-computation nodejs oblivious-transfer typescript verilog

Last synced: 15 Dec 2024

https://github.com/tdholmes/digitaldesign-pong

Verilog Pong game designed for Digital Design in December of 2013.

pong verilog

Last synced: 02 Dec 2024

https://github.com/mssola/hdl

Playing around with Hardware Description Languages.

hdl systemverilog verilog

Last synced: 29 Nov 2024

https://github.com/aliiiw/computer-architecture-lab

Implement Mips cpu with Verilog

forwarding mips pipeline verilog

Last synced: 02 Dec 2024

https://github.com/chaseruskin/setup-orbit

GitHub Action to install Orbit

action continuous-integration hdl systemverilog utilities verilog vhdl

Last synced: 27 Nov 2024

https://github.com/dpieve/university

A resource for students learning programming and personal reference.

assembly cpp haskell haskell-exercises java matlab prolog python shell unifei-university verilog

Last synced: 22 Dec 2024

https://github.com/sergz72/fpga

FPGA related stuff

assembler assembly-language bytecode-compiler cpu cyclone forth forth-cpu forth-language fpga fpga-programming gowin java java-cpu risc-v verilog

Last synced: 28 Nov 2024

https://github.com/dyna-bytes/fpga_winter_internship_2020

[Korea University Elementary Particle Physics Lab] Hardware control research using FPGA

fpga rtl verilog vhdl

Last synced: 02 Dec 2024

https://github.com/dyna-bytes/fisr

Specialized FPU for Fast Inverse Square Root Algorithm

fpu verilog

Last synced: 02 Dec 2024

https://github.com/toruniina/brainfxck-circuit

run brainfxck on FPGA

brainfuck verilog

Last synced: 08 Dec 2024

https://github.com/guntas-13/verilog

Compilation of all the Verilog Assignments in the course ES204 - Digital Systems (Spring 2024) - Prof. Joycee Mekie

verilog verilog-hdl

Last synced: 03 Dec 2024

https://github.com/kulp/tappy

tappy is a tiny Verilog driver for PS/2 keyboards, for use in FPGAs

fpga verilog

Last synced: 16 Dec 2024

https://github.com/harikrishnan669/verilog

KTU S4 DIGITAL LAB PROGRAMS (VERILOG)

cse ktu-s4-cse verilog

Last synced: 28 Nov 2024

https://github.com/et312/custom_cpu

Custom 16-bit RISC-based CPU with custom control unit, ALU, and memory block designs

fpga verilog

Last synced: 16 Dec 2024

https://github.com/abshar-shihab/the-fast-matrix-multiplication-on-fpga

This repository explores efficient matrix multiplication on FPGA hardware. Communication between the PC and FPGA is implemented through UART.

fpga nexus-3 pipelined uart verilog

Last synced: 23 Dec 2024

https://github.com/wassimhedfi/fpga_adc_pwm_motorcontrol

This repository contains the implementation of a motor speed control system using an FPGA. The speed is adjusted dynamically through a potentiometer, leveraging ADC for analog-to-digital conversion and PWM for precise motor control.

adc de10-lite fpga html motor-speed pwm verilog vhdl

Last synced: 04 Dec 2024

https://github.com/princeranjan03/imageencryption_i-chip

This project focuses on creating a hardware-based encryption and decryption system that implements the Data Encryption Standard (DES) algorithm.

cipher cryptography data-encryption data-encryption-standard encoding encryption-decryption fpga image image-processing opencv rtldesign source-coding verilog verilog-hdl verilog-project vivado xilinx xilinx-vivado

Last synced: 04 Dec 2024

https://github.com/vlad-ivanov-name/verilog-zeroall

Resets all register to zero in a Verilog design

modelsim verilog

Last synced: 04 Dec 2024

https://github.com/fuwn/iverilog-test-bench

☀️ Icarus Verilog Test-bench Template

de10 icarus-verilog verilog

Last synced: 10 Dec 2024

https://github.com/andrejchoo/cpldctrum

ZX Spectrum clone on CPLD

cpld divmmc verilog zx-spectrum

Last synced: 11 Dec 2024

https://github.com/andrejchoo/avr_like_core_on_verilog

Soft core with support for the AVR8 instructions on verilog

avr soft-core verilog

Last synced: 11 Dec 2024

https://github.com/pseudoincorrect/verilog_labs

Verilog labs

c dsp soft-cpu verilog

Last synced: 16 Dec 2024

https://github.com/seojuncha/fromthetransistor-fork

geohot's fromthetransistor project. Create a repo on my own because of the contribution map!!

assembler assembly c compiler fromthetransistor python uart verilog

Last synced: 11 Dec 2024

https://github.com/skpro-glitch/resume

Find my resume, encapsulating my most prominent projects and experiences relevant for an entry level Hardware Engineering role. - Soham Kapur

algorithms-and-data-structures cadence cadence-virtuoso drone electronics-engineering java java-programming ltspice matlab soham-kapur sohamkapur team-aviators-international uav verilog verilog-hdl verilog-processor vit-chennai vit-university vitc vitchennai

Last synced: 12 Dec 2024

https://github.com/abstractmachines/verilog-shift-register

A shift register in Verilog. Bidirectional pin use.

embedded-systems hardware shift-register verilog

Last synced: 12 Dec 2024

https://github.com/mtaciano/fpgmips

Um processador baseado na arquitetura MIPS 32bits no FPGA DE2-115.

fpga mips processor verilog

Last synced: 12 Dec 2024

https://github.com/rehankarthikchandralal/implementation-of-a-configurable-neural-processing-unit-with-input-and-weight-stationary-dataflows

Used Verilog to design an entire NPU that supports two different kinds of dataflows to enable data reuse in order to reduce power consumption and resource utilization

neural-network-hardware verilog

Last synced: 17 Dec 2024

https://github.com/shuregg/riscv-simple-cpu

Creating a risc-v processor

cpu risc-v riscv riscv32 rtl systemverilog verification verilog verilog-hdl

Last synced: 13 Dec 2024

https://github.com/shuregg/fpga-practicum

learning about FPGA

fpga fpga-programming rtl systemverilog verilog vivado xilinx

Last synced: 13 Dec 2024

https://github.com/dev-ritik/calculator

Xilinx college project

calculator college-project gui java-applet verilog xilinx

Last synced: 03 Dec 2024

https://github.com/miku-218525/asic_lab

verilog

Last synced: 25 Dec 2024

https://github.com/justin-marian/tiny-risc-v

Minimalist RISC-V with a five-stage pipeline. It serves as a platform for understanding processor design principles.

isa-architecture risc-v-architecture verilog

Last synced: 27 Dec 2024

https://github.com/3-o-3/cod5

Public Domain (⊄) Computer on FPGA

fpga fpga-soc public-domain ternary ternary-computer verilog

Last synced: 18 Dec 2024

https://github.com/justin-marian/fsm-vending-machine

FSM vending machine, it dispenses products based on user input and provides change based on the money introduced.

fsm vending-machine-proplem verilog

Last synced: 27 Dec 2024

https://github.com/calint/tang-nano-20k--riscv

riscv rv32i tang-nano-20k verilog

Last synced: 11 Nov 2024

https://github.com/shiro-raven/verilog-mips

A verilog-based MIPS processor with pipelining

assembly mips mips-architecture verilog

Last synced: 05 Dec 2024

https://github.com/calint/riscv

experiments implementing a risc-v cpu to gain experience with verilog and minimalistic cpu design

cmod-s7 cpu fpga iverilog risc-v riscv32i verilog vivado

Last synced: 11 Nov 2024

https://github.com/calint/zen-one

experimental retro 16 bit cpu written in verilog xilinx vivado intended for fpga cmod s7 from digilent

16-bit cmod-s7 cpu fpga iverilog verilog vintage vivado

Last synced: 11 Nov 2024

https://github.com/calint/tang-nano-9k--riscv

RISC-V rv32i implementation on Tang Nano 9K

risc-v rv32i tang-nano-9k verilog

Last synced: 11 Nov 2024