https://github.com/platformio/platform-lattice_ice40

Lattice iCE40: development platform for PlatformIO

fpga icestorm lattice platformio platformio-platform verilog

Last synced: 07 Oct 2024

https://github.com/mbtaylor1982/resdmac

Verilog code to replace the Commodore SDMAC found in the A3000

altera-fpga amiga amiga-hardware intel-fpga kicad open-source quartus verilog

Last synced: 13 Dec 2024

https://github.com/ustb-owl/Uranus

Uranus MIPS processor by MaxXing & USTB NSCSCC team

cpu fpga mips risc verilog

Last synced: 28 Oct 2024

https://github.com/chili-chips-ba/wireguard-fpga

Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door is wide open for backdoor scrutiny, be it related to RTL, embedded, build, bitstream or any other aspect of design and delivery package. Bujrum!

cocotb embedded fpga iss risc-v rtl verilator verilog vpn vproc wireguard

Last synced: 13 Dec 2024

https://github.com/ultraembedded/core_usb_fs_phy

USB Full Speed PHY

fpga usb verilog

Last synced: 12 Nov 2024

https://github.com/hrvach/edsac

FPGA Verilog implementation of 1949 EDSAC Computer with animated tape reader, panel, teleprinter and CRT scope

edsac emulation fpga mister misterfpga papertape retrocomputing verilog vintage-computers

Last synced: 28 Dec 2024

https://github.com/ultraembedded/core_spiflash

SPI-Flash XIP Interface (Verilog)

axi4 fpga spi spi-flash verilog xip

Last synced: 12 Nov 2024

https://github.com/fpgawars/apio-examples

:seedling: Apio examples

apio examples verilog

Last synced: 24 Dec 2024

https://github.com/Nic30/hwtLib

hardware library for hwt (= ipcore repo)

fpga hardware-designs rtl verilog vhdl

Last synced: 09 Nov 2024

https://github.com/nic30/hwtlib

hardware library for hwt (= ipcore repo)

fpga hardware-designs rtl verilog vhdl

Last synced: 01 Jan 2025

https://github.com/paebbels/picoblaze-library

The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a Chip (SoC or SoFPGA).

assembler fpga hardware hardware-architectures hardware-designs hardware-libraries hdl picoblaze-devices picoblaze-library poc-library simulation soc synthesis verilog vhdl

Last synced: 08 Nov 2024

https://github.com/ahirsharan/32-Bit-Floating-Point-Adder

Verilog Implementation of 32-bit Floating Point Adder

verilog vlsi xilinx

Last synced: 10 Nov 2024

https://github.com/ultraembedded/core_usb_bridge

USB -> AXI Debug Bridge

axi4-lite fpga usb usb-cdc verilog

Last synced: 12 Nov 2024

https://github.com/wyvernSemi/riscV

Open source ISS and logic RISC-V 32 bit project

32-bit c-plus-plus co-simulation cpu-model embedded-systems fpga iss linux processor risc-processor risc-v soft-core verilog

Last synced: 27 Oct 2024

https://github.com/Archfx/FPGA-stereo-Camera-Basys3

Integration of two camera 📷 modules to Basys 3 FPGA

fpga verilog vhdl

Last synced: 26 Oct 2024

https://github.com/mediaic/crash_course_for_new_members

Deep Learning & VLSI Crash Course for New Members

deep-learning opencv python pytorch systemverilog verilog vlsi

Last synced: 20 Nov 2024

https://github.com/nic30/hdlconvertorast

Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator

codegen codegenerator fpga python systemc systemverilog verilog vhdl

Last synced: 31 Dec 2024

https://github.com/jeffdecola/my-verilog-examples

A place to keep my synthesizable verilog examples.

asic asic-design fpga gtkwave hardware hardware-architecture hardware-description-language hdl iverilog simulator synthesis synthesize systemverilog verilog verilog-simulator vivado waveform xilinx

Last synced: 10 Dec 2024

https://github.com/sabertazimi/hust-lab

Labs for Computer Science: C, Assembly, Data Structure, CSAPP, HSI, MATLAB, Digital Logic, Verilog, Compilers, Operating Systems

algorithm assembly c compiler computer-science data-structrues digital-logic functional-programming hust hust-lab lab matlab operating-system verilog

Last synced: 07 Nov 2024

https://github.com/grebe/ofdm

Chisel Things for OFDM

chip-generator chisel chisel3 firrtl rtl scala verilog

Last synced: 27 Oct 2024

https://github.com/hrvach/life_mister

Conway's Game of Life in FPGA

conways-game-of-life fpga game hdmi misterfpga verilog video

Last synced: 28 Dec 2024

https://github.com/thoughtworks/hardposit-chisel3

Chisel library for Unum Type-III Posit Arithmetic

chisel chisel3 firrtl floating-point fpu posit rtl scala unum verilog

Last synced: 09 Nov 2024

https://github.com/drom/reqack

🔁 elastic circuit toolchain

hacktoberfest hardware-description-language hdl verilog

Last synced: 02 Nov 2024

https://github.com/ultraembedded/core_usb_uart

USB serial device (CDC-ACM)

fpga serial-port uart usb-cdc usb-device usb-serial verilog

Last synced: 12 Nov 2024

https://github.com/thesupercd/8bit_microcomputer_verilog

This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a breadboard, it has the functionalities of his computer and modelled using Verilog HDL. This project was developed as a Mini Project in Digital Systems course in my 3rd semester at IIT Palakkad.

8bit ben-eater ben-eaters-cpu iverilog verilog verilog-code verilog-hdl verilog-project

Last synced: 18 Dec 2024

https://github.com/chipsalliance/f4pga-sdf-timing

Python library for working Standard Delay Format (SDF) Timing Annotation files.

interconnect-delays python-sdf-timing sdf symbiflow verilog

Last synced: 05 Nov 2024

https://github.com/mbuesch/crcgen

Generator for CRC HDL code (VHDL, Verilog, MyHDL)

crc crc-algorithms crc-calculation crc32 myhdl verilog vhdl

Last synced: 31 Oct 2024

https://github.com/skyzh/mips-cpu

💻 A 5-stage pipeline MIPS CPU implementation in Verilog.

computer-architecture cpu mips verilog

Last synced: 11 Nov 2024

https://github.com/mmicko/enigmafpga

Enigma in FPGA

blackice fpga goboard ice40 verilog yosys

Last synced: 05 Dec 2024

https://github.com/mmicko/enigmaFPGA

Enigma in FPGA

blackice fpga goboard ice40 verilog yosys

Last synced: 10 Nov 2024

https://github.com/buhe/bugu-computer

💻 Build own computer by fpga.

fpga hdl nand2tetris own tutorials verilog

Last synced: 01 Jan 2025

https://github.com/ultraembedded/fpga_test_soc

A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)

cortex-m0 fpga fpga-soc gpio risc-v spi verilog

Last synced: 12 Nov 2024

https://github.com/hukenovs/math

Useful m-scripts for DSP (CIC, FIR, FFT, Fast convolution, Partial Filters etc.)

cic digital-signal-processing dsp fast-convolutions fast-fourier-transform fft fir fpga m-scripts math matlab octave verilog vhdl

Last synced: 19 Nov 2024

https://github.com/nic30/hwthls

LLVM based HLS library for HWToolkit (hardware devel. toolkit)

compiler fpga hls llvm systemverilog verification verilog vhdl

Last synced: 16 Nov 2024

https://github.com/jameshanlon/netlist-paths

A library and command-line tool for querying a Verilog netlist.

netlist-paths systemverilog verilog

Last synced: 17 Nov 2024

https://github.com/ultraembedded/minispartan6-audio

miniSpartan6+ (Spartan6) FPGA based MP3 Player

audio fpga mp3player risc-v rv32im sd-card spartan6 verilog verilog-project

Last synced: 12 Nov 2024

https://github.com/delhatch/spectrum

Spectrum analyzer system using a 512-point FFT, in a Cyclone IV FPGA. Reads i2s audio from the codec and then does all FFT/VGA functions. Nios just reads the FFT result and draws the display bars. VGA frame buffer on-chip. VGA signals generated on-chip. See the included video files to watch it in action.

altera audio-analysis de2-115 fft fpga rtaudio spectrum-analyzer verilog vga vga-frame-buffer

Last synced: 13 Nov 2024

https://github.com/ultraembedded/core_ftdi_bridge

FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge

axi4 communications-blocks fpga ftdi ftdi-232h verilog

Last synced: 12 Nov 2024

https://github.com/phillbush/legv8

LEGv8 CPU implementation and some tools like a LEGv8 assembler

awk hennessy hennessy-and-patterson legv8 legv8-arm patterson pipeline-cpu pipeline-processor single-cycle single-cycle-processor verilog

Last synced: 22 Nov 2024

https://github.com/bensampson5/libsv

An open source, parameterized SystemVerilog digital hardware IP library

asic asic-library digital-design fpga fpga-library hardware hardware-designs hardware-libraries hdl ip systemverilog verilog

Last synced: 17 Nov 2024

https://github.com/SLink-Protocol/S-Link

An Open Source Link Protocol and Controller

asic chiplets fpga protocol systemverilog verilog

Last synced: 10 Nov 2024

https://github.com/chaseruskin/orbit

An agile package manager and extensible build tool for HDLs

agile agile-development build-tool command-line-tool cross-platform hardware hdl package-manager systemverilog verilog vhdl

Last synced: 14 Nov 2024

https://github.com/ben-marshall/croyde-riscv

A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.

cpu crypto cryptography formal-verification micro-controller microcontroller mit-license risc risc-v riscv64 systemverilog verilator verilog yosys

Last synced: 29 Nov 2024

https://github.com/SymbiFlow/sphinx-verilog-domain

Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.

hdl rtl sphinx sphinx-domain sphinx-extension systemverilog verilog verilog-library

Last synced: 17 Nov 2024

https://github.com/dalance/svls-vscode

SystemVerilog language server client for Visual Studio Code

language-server systemverilog verilog visual-studio-code

Last synced: 10 Nov 2024

https://github.com/ultraembedded/core_ulpi_wrapper

ULPI Link Wrapper (USB Phy Interface)

fpga ulpi usb usb-interface verilog

Last synced: 12 Nov 2024

https://github.com/racerxdl/biggateboy

WIP Big FPGA Gameboy

fpga gameboy verilog

Last synced: 26 Dec 2024

https://github.com/mr-bossman/kisc-v

KISCV, a KISS principle riscv32i CPU

cpu hdl risc-v riscv riscv32 verilog

Last synced: 18 Dec 2024

https://github.com/RISCuinho/core

**RISC**uinho - A scratch in the possibilities in the universe of microcontrollers

risc-v rv32i verilog

Last synced: 08 Nov 2024

https://github.com/sdasgup3/parallel-processor-design

Super scalar Processor design

assembler bison branch-prediction bypassing flex forwarding instruction-level-parallelism instruction-set instruction-set-architecture mnemonics opcode parallel-computing pipeline-cpu pipeline-processor processor processor-architecture processor-simulator superscalar verilog verilog-hdl

Last synced: 23 Dec 2024

https://github.com/mmicko/grom8

GROM-8 CPU

codedive cpu ice40 verilog

Last synced: 15 Oct 2024

https://github.com/enigmacurry/sap

A very simple computer written in Verilog, with a Python test bench

ben-eater fpga sap-1 verilog

Last synced: 24 Dec 2024

https://github.com/j3soon/handwritten-digit-recognition-painter

A handwritten digit recognition painter implementation on Basys 3 Artix-7 FPGA using Verilog.

artix-7 basys3 deep-learning hardware painter verilog

Last synced: 07 Dec 2024

https://github.com/siamumar/tinyaes

aes fpga sbox verilog

Last synced: 10 Nov 2024

https://github.com/ultraembedded/core_usb_sniffer

USB capture IP

usb-debugging usb2 verilog

Last synced: 12 Nov 2024

https://github.com/sadrasabouri/cordic

Implementation of CORDIC Algorithms Using Verilog

asic cordic cordic-algorithm fpga tanh verilog

Last synced: 16 Nov 2024

https://github.com/wohali/vcd_parsealyze

A Value Change Dump (VCD) file parser and analyzer

eda python vcd verilog

Last synced: 01 Oct 2024

https://github.com/ultraembedded/cortex_m0_wrapper

Cortex-M0 DesignStart Wrapper

armv6 axi4 cortex-m0 fpga verilog

Last synced: 12 Nov 2024

https://github.com/buaadreamer/buaa-co-2020

2020年北航计组课设代码 This is the BUAA Computer Orgnization code project files.

computer-organization cpu logisim mars mips verilog

Last synced: 06 Dec 2024

https://github.com/chipsalliance/f4pga-xc7-bram-patch

Tool for updating the contents of BlockRAMs found in Xilinx 7 series bitstreams.

bitstream fasm prjxray prjxray-bram symbiflow verilog vivado

Last synced: 05 Nov 2024

https://github.com/freand76/digsim

An interactive digital logic simulator with verilog support (Yosys)

logic python rtl simulation simulator vcd verilog yosys

Last synced: 17 Nov 2024

https://github.com/alangarf/tm1638-verilog

A basic verilog driver for the TM1638 LED and key matrix chip

arachne-pnr ice40 icestorm tm1638 verilog yosys

Last synced: 07 Dec 2024

https://github.com/b1f6c1c4/deep-darkfantasy

Global Dark Mode for ALL apps on ANY platforms.

dark-mode dark-mode-toggle dark-theme fpga verilog verilog-hdl vivado xilinx zynq zynq-7000

Last synced: 16 Dec 2024

https://github.com/RipperJ/RISC-V_CPU

RISC-V 32i Pipeline CPU and Assembler

assembler cpu fpga pipeline-cpu risc-v simulation verilog

Last synced: 21 Nov 2024

https://github.com/kittennbfive/5A-75B-tools

a collection of tools made while messing with the Colorlight 5A-75B V7.0 and some notes using ECP5 with Yosys

5a-75b chubby75 colorlight ecp5 fpga nextpnr nextpnr-ecp5 verilog yosys

Last synced: 13 Nov 2024

https://github.com/geraked/verilog-rle

Verilog Implementation of Run Length Encoding for RGB Image Compression

compression-algorithm computer-engineering fpga fpga-programming geraked image-compression image-processing ise matlab rabist rle rle-compression-algorithm run-length-encoding student-project verilog verilog-code verilog-hdl xilinx xilinx-fpga yazd-university

Last synced: 09 Nov 2024

https://github.com/perehinik/sdram_controller

Verilog SDR SDRAM controller for FPGA Xilinx and Lattice

fpga lattice sdram verilog xilinx

Last synced: 31 Dec 2024

https://github.com/jbush001/mitecpu

Minimal microprocessor

cpu fpga hardware verilog

Last synced: 15 Oct 2024

https://github.com/hoangsonww/digital-design-labs

🖥️ A collection of SystemVerilog modules and Assembly programs. This repo includes examples of decoders, encoders, binary adders, and interactive games such as Guessing Game implemented in hardware description and assembly languages, illustrating practical applications in digital systems and microprocessor interfacing.

3to8decoder alu arithmetic-logic-unit assembly carry-look-ahead-adder carry-select-adder counter decoder encoder finite-state-machine guessing-game microcontroller microcontroller-programming pic16f84a system-design systemverilog verilog

Last synced: 14 Nov 2024

https://github.com/charmve/accann

🐆 A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration for *AdderNet*

accelerator addernet asic charmve cnn deep-learning fpga fpga-hardware ghostnet gpu-acceleration hardware hardware-acceleration neurips paper verilog

Last synced: 15 Nov 2024

https://github.com/jn513/risco-5

Multi-cycle RISC-V processor with RV32I/E[M] implementation, built during a few days off.

arquitetura fpga risc-v riscv riscv32 verilog verilog-hdl

Last synced: 15 Dec 2024

https://github.com/sunaku/ruby-vpi

Ruby interface to IEEE 1364-2005 Verilog VPI

hardware-designs simulation testing-tools verification verilog

Last synced: 16 Oct 2024

https://github.com/Elphel/vdt-plugin

mirror of https://git.elphel.com/Elphel/vdt-plugin

cocotb eclipse eclipse-plugin gtkwave icarus-verilog ide quartus verilog vivado

Last synced: 29 Nov 2024

https://github.com/princetonuniversity/maple

MAPLE's hardware-software co-design allows programs to perform long-latency memory accesses asynchronously from the core, avoiding pipeline stalls, and enabling greater memory parallelism (MLP).

memory-accelerators memory-access memory-latency programmable-block rtl specialized-hardware verilog

Last synced: 20 Nov 2024

https://github.com/semify-eda/fstdumper

Verilog VPI module to dump FST (Fast Signal Trace) databases

simulator systemverilog verilog vpi waveform

Last synced: 09 Nov 2024

https://github.com/addisonelliott/scic

Project of Addison Elliott and Dan Ashbaugh to create IC layout of 32-bit custom CPU used in teaching digital design at SIUE.

asic cadence cpu digital gate icarus-verilog rtl simulation synthesis tcl verilog

Last synced: 08 Dec 2024

https://github.com/chaseruskin/legoHDL

An experimental package manager and development tool for Hardware Description Languages (HDL).

digital-design digital-logic fpga hardware-description-language hardware-design hdl package-manager verilog vhdl

Last synced: 17 Nov 2024

https://github.com/kristoff-starling/projectn-cpu

Single Cycle and Pipeline CPU of RISC-V Architecture designed for Digital Design and Computer Organization Experiments 2021, NJU

cpu pipeline riscv32 verilog

Last synced: 28 Oct 2024

https://github.com/jbush001/waveview

Digital Waveform Viewer

tool verilog vhdl waveform

Last synced: 15 Oct 2024

https://github.com/chaseruskin/legohdl

An experimental package manager and development tool for Hardware Description Languages (HDL).

digital-design digital-logic fpga hardware-description-language hardware-design hdl package-manager verilog vhdl

Last synced: 14 Nov 2024

https://github.com/dramforever/finlog

Compiling finite generators to digital logic. WIP

compiler digital-logic haskell verilog

Last synced: 18 Nov 2024

https://github.com/wavedrom/doppler

Doppler effect on WaveForms

hacktoberfest verilog vhdl

Last synced: 09 Nov 2024

https://github.com/liolok/hdu_co_guide

HDU Computer Organization Course Design Beginner Guide - 杭电计组课设新手指南

artix-7 computer-organization course-design verilog vivado

Last synced: 20 Nov 2024

https://github.com/darklife/udarkrisc

u[Dark]RISC -- "micro-darkrisc" -- an early 16-bit micro-RISC processor defined before DarkRISCV

core cpu fpga processor processor-design risc rtl softcore verilog

Last synced: 15 Nov 2024

https://github.com/benitoss/cyclonev_unamiga_v2

Cyclone V FPGA board for UnAmiga project with new addon 6 Buttons Megadrive Joystick

verilog vhdl

Last synced: 24 Dec 2024

https://github.com/jbush001/fpgawhack

Video Effects on VGA

fpga hardware verilog

Last synced: 02 Dec 2024

https://github.com/aditeyabaral/ddco-lab-ue18cs207

A repository containing the source codes for the Digital Design and Computer Organization Laboratory course (UE18CS2) at PES University.

computer-organization digital-design icarus-verilog logic-programming verilog verilog-code

Last synced: 16 Nov 2024

https://github.com/perehinik/logic_analyzer_fpga_config

Vivado project for Xilinx Artix FPGA, used in logic analyzer

fpga verilog vivado xilinx

Last synced: 31 Dec 2024

https://github.com/doctorwkt/ulx3s-blinky

A blinky project for the ULX3S v3.0.3 FPGA board

fpga nextpnr prjtrellis verilog yosys

Last synced: 27 Dec 2024

https://github.com/sadrasabouri/802.11a

Software-Hardware Implementation of IEEE 802.11a Wifi Standard

802-11 hardware hardware-designs matlab verilog wifi

Last synced: 11 Oct 2024

https://github.com/robroyce/fpga_mouse_controller_basys3

USB-to-PS2 mouse controller for FPGAs written in Verilog. Performs clock division, signal sampling, processing, error checking, and validation. Includes Xilinx Basys 3 target configuration.

mouse ps2-clock signal verilog

Last synced: 20 Dec 2024

https://github.com/wvangansbeke/high-level-synthesis

Convert C files into Verilog

c-plus-plus high-level-synthesis verilog

Last synced: 07 Nov 2024

https://github.com/jiegec/verilog-lang

A hand-written recursive decent Verilog parser.

rust verilog

Last synced: 09 Nov 2024

https://github.com/theonekevin/icarusext

iverilog extension for Visual Studio Code to satisfy the needs for an easy testbench runner. Includes builtin GTKWave support.

gtkwave icarus-verilog verilog verilog-testbenches vscode-extension

Last synced: 19 Oct 2024

https://github.com/lethalbit/discretize

A Yosys pass and technology library + scripts for implementing a HDL design in discretie FETs for layout in KiCad

electronics hdl verilog yosys-plugin

Last synced: 06 Nov 2024

https://github.com/Archfx/FPGA-DepthMap-Basys3

Real Time depth map 🏞️ generation using SSD algorithm on low end Basys 3 FPGA. Support 320x240 and 160x120 resolutions.

depth-map fpga robotics verilog

Last synced: 26 Oct 2024

https://github.com/cceroici/Stochastic-Neural-Network

Fully Hardware-Based Stochastic Neural Network

ai fpga hardware network neural stochastic stochastic-computing verilog

Last synced: 15 Oct 2024

https://github.com/chipsalliance/f4pga-xc-fasm2bels

Library to convert a FASM file into BELs importable into Vivado.

artix-7 bitstream fasm symbiflow tcl verilog vivado

Last synced: 23 Dec 2024

https://github.com/wissance/2dimageprocessing

2d Images processing system with FPGA (Zynq 7k) from two dragster linescanner (DR-2k-7)

2d 2d-scaner awaiba cmosis computer-vision dr-2k-7 dragster fpga frequency-analysis frequency-measurment image-processing optical optical-mark-recognition optical-measurements optical-sensors optical-system optics verilog xilinx-fpga xilinx-vivado

Last synced: 17 Dec 2024

https://github.com/delhatch/red_tracker

Uses the D8M camera module, then processes the image to detect red objects, and then overlay an x,y crosshair on the largest red object. See the video. Pure Verilog. (No soft-core processor.)

altera de2-115 fpga image-processing verilog vga vga-controller

Last synced: 13 Nov 2024