https://github.com/prinuvinod/digital-lab

These are some Verilog Programs

digital verilog

Last synced: 06 Jan 2025

https://github.com/cepdnaclk/e18-co502-rv32im-pipeline-implementation-group4

Single-cycle MIPS-like processor with a memory subsystem including a cache.

computer-architecture risc-v verilog

Last synced: 11 Jan 2025

https://github.com/assem-elqersh/mips-processor-designs

Comprehensive repository containing Verilog implementations of MIPS processors. Includes both single-cycle and multi-cycle architectures, each in separate directories, with full simulation testbenches and modular design components for educational and development purposes.

computer-architecture educational hardware-designs mips mips-architecture processor-design simulation verilog

Last synced: 27 Jan 2025

https://github.com/fuwn/iverilog-test-bench

☀️ Icarus Verilog Test-bench Template

de10 icarus-verilog verilog

Last synced: 05 Feb 2025

https://github.com/soham9284/smart-home-automation-system

The Smart Home Automation System is a comprehensive solution that integrates sensors, manual controls, and automated logic to manage lighting, temperature, security, and emergency responses efficiently.

fpga fpga-board verilog xilinx-vivado

Last synced: 02 Feb 2025

https://github.com/rainingcomputers/srp16

SRP16 is free and open ISA for 16-bit CPUs and Microcontrollers.

cpu instruction-set-architecture isa isa-specification microcontrollers open-embedded open-isa risc soft-core verilog

Last synced: 14 Feb 2025

https://github.com/seojuncha/fromthetransistor-fork

geohot's fromthetransistor project with a little modification.

assembler assembly c compiler fromthetransistor python uart verilog

Last synced: 05 Feb 2025

https://github.com/j-m-li/3o3

Ternary CPU for EPROM and FLASH memories

eprom public-domain verilog

Last synced: 01 Feb 2025

https://github.com/skpro-glitch/resume

Find my resume, encapsulating my most prominent projects and experiences relevant for an entry level Hardware Engineering role. - Soham Kapur

algorithms-and-data-structures cadence cadence-virtuoso drone electronics-engineering java java-programming ltspice matlab soham-kapur sohamkapur team-aviators-international uav verilog verilog-hdl verilog-processor vit-chennai vit-university vitc vitchennai

Last synced: 05 Feb 2025

https://github.com/jminjares4/digital-system-2-template

Digital System 2 Template

digital-design verilog

Last synced: 10 Jan 2025

https://github.com/sofiavalos/verilog_ethernet_10g_mac

Bloques y bancos de pruebas MAC para Ethernet 10G.

ethernet mac verilog

Last synced: 06 Feb 2025

https://github.com/avantikaadiyodi/fpga-based-fault-analyzer-for-industrial-motors

cpp dsp fft fpga instrumentation matlab motor verilog

Last synced: 09 Feb 2025

https://github.com/saifalomari99/fpga_projects_saifalomari

This Repository is to showcase Saif Alomari's FPGA projects. Includes 25 high-level FPGA projects in various HDLs.

fpga systemverilog verilog

Last synced: 28 Dec 2024

https://github.com/clementkim/logic-circuit-verilog

아주대학교 논리회로 - Verilog를 이용한 프로젝트 코드

logic-circuit verilog

Last synced: 08 Feb 2025

https://github.com/niw/chisel_test

A simple Chisel test project for myself to learn Chisel and FPGA.

chisel3 fpga orangecrab scala tinyfpga verilog

Last synced: 06 Jan 2025

https://github.com/lasithaamarasinghe/uart-implementation-in-fpga

This is a group assignment done under semester 4 module EN2111:Electronic Circuit Design, .

fpga quartus-prime uart verilog

Last synced: 10 Jan 2025

https://github.com/miku-218525/asic_lab

verilog

Last synced: 25 Dec 2024

https://github.com/dev-ritik/calculator

Xilinx college project

calculator college-project gui java-applet verilog xilinx

Last synced: 30 Jan 2025

https://github.com/javiidiazglez/ec

Estructuras de Computadores

verilog

Last synced: 01 Jan 2025

https://github.com/calint/znxcr

experimental retro 16 bit cpu written in verilog xilinx vivado intended for fpga Cmod S7 from Digilent

16-bit cmod-s7 cpu fpga verilog

Last synced: 10 Jan 2025

https://github.com/calint/tang-nano-9k--riscv

RISC-V rv32i implementation on Tang Nano 9K

risc-v rv32i tang-nano-9k verilog

Last synced: 10 Jan 2025

https://github.com/calint/riscv

experiments implementing a risc-v cpu to gain experience with verilog and minimalistic cpu design

cmod-s7 cpu fpga iverilog risc-v riscv32i verilog vivado

Last synced: 10 Jan 2025

https://github.com/mongshil553/digital-engineering-verilog-assignments

Sophomore 2021 1st Semester Digital Engineering Verilog Assignments

fpga-programming verilog xilinx-vivado

Last synced: 13 Jan 2025

https://github.com/urish/tt06-spell

A minimal, stack-based programming language created for The Skull CTF

tinytapeout verilog wizardry

Last synced: 11 Jan 2025

https://github.com/mohamad-shosha/alu-verilog-proteus

This 4-bit ALU design project has been implemented as part of the [Computer Aided Design] in the university , where we applied Verilog for hardware design and Proteus for simulation.

proteus verilog

Last synced: 28 Dec 2024

https://github.com/arefin994/bitstreamos

BitStreamOS --- A custom-designed MIPS CPU and operating system built from scratch. Features include a custom instruction set, assembler for converting assembly code to binary, CPU simulation with test benches, waveform visualization, and a basic OS implementation.

asm cpu mips-assembly os verilog

Last synced: 01 Jan 2025

https://github.com/youseftareq33/digital_buildcombinationalcircuit_1

Using Verilog HDL on Quartus application build combinational circuit

combinational-circuit verilog

Last synced: 24 Dec 2024

https://github.com/cosminpopescu14/fpga

Sisteme FPGA

fpga verilog

Last synced: 25 Dec 2024

https://github.com/rpigor/tpsim

TPSim (Timing and Power Simulator) is a gate-level circuit simulator with timing and power estimation capabilities

eda power-analysis simulator timing-analysis verilog

Last synced: 06 Jan 2025

https://github.com/aledpl5/rock-paper-scissors-circuit

Uni project about the game rock-paper-scissors

blif circuit datapath datapath-design finate-state-machine sis systemverilog verilog

Last synced: 05 Jan 2025

https://github.com/camilaqpereira/oficina-verilog-siecomp

Neste repositórios estão disponibilizados todos os arquivos utilizados na Oficina Introdução ao Verilog Comportamental ministrado na XXXI SIECOMP (UEFS). Além disso, estão listados múltiplos recursos para estudo da linguagem.

oficina verilog verilog-code verilog-hdl

Last synced: 23 Jan 2025

https://github.com/namberino/simple-uart

Simple UART implementation in FPGA

fpga uart verilog

Last synced: 20 Jan 2025

https://github.com/kassane/fpga_course

Testing conducted during verilog studies

fpga verilog

Last synced: 13 Jan 2025

https://github.com/guntas-13/verilog

Compilation of all the Verilog Assignments in the course ES204 - Digital Systems (Spring 2024) - Prof. Joycee Mekie

verilog verilog-hdl

Last synced: 30 Jan 2025

https://github.com/guntas-13/mips-processor-basys3

Full FPGA Implementation of 32-bit FSM-based Multi-State MIPS Processor

mips-assembly mips-processor processor-architecture verilog

Last synced: 30 Jan 2025

https://github.com/lemongrb/digitaldesignwithverilog

Simple circuits designed with verilog

asic behavioural dataflow design digitalsystems fpga structural verilog verilog-code verilog-project verilogprojects

Last synced: 10 Jan 2025

https://github.com/calint/tang-nano-20k--riscv--cache-sdram

RISC-V implementation of rv32i for FPGA board Tang Nano 20K utilizing on-board burst SDRAM and flash

fpga risc-v rv32i systemverilog tang-nano-20k verilog

Last synced: 03 Jan 2025

https://github.com/andrejchoo/fpga_wav_player

A simple project for playing wav files on FPGA or CPLD

fpga spi-flash verilog wav

Last synced: 03 Jan 2025

https://github.com/kayejd/nexysa7-fpga-programming

Embedded Programming Projects

embedded-systems fpga-programming verilog vivado

Last synced: 17 Jan 2025

https://github.com/kayejd/hvac-system

School Related Project

capstone digital digital-signal-processing engineering-design verilog

Last synced: 17 Jan 2025

https://github.com/thedhruvrawat/comparch

This repository contains all the laboratory coursework for the course CS F342: Computer Architechture at BITS Pilani, Pilani Campus (Fall '22)

computer-architecture verilog

Last synced: 03 Jan 2025

https://github.com/davidf1000/sistemdigital_vhdl

Final Project for Digital System Lab. Flappy Bird Imitation Game created using VHDL for FPGA DE1.

fpga quartus verilog vhdl

Last synced: 11 Jan 2025

https://github.com/shpegun60/open_std_fpga

This std libraries on fpga

fpga-std standard-library-fpga verilog

Last synced: 18 Jan 2025

https://github.com/strwdr/MaximatorZXSpectrum

ZX Spectrum implementation for maximator board

board fpga hdl max10 maximator nios soc verilog zx zx-spectrum

Last synced: 24 Oct 2024

https://github.com/susiejojo/sobel_filter

Sobel filter for edge detection in images supporting parallel processing using Verilog on Xilinx ISE 13.4

hdl sobel-filter verilog xilinx-ise

Last synced: 09 Feb 2025

https://github.com/ted-xie/icesuite

One-stop-shop for all the tools you need to get started with the iCE40 breakout board.

fpga ice40 lattice verilog yosys

Last synced: 12 Jan 2025

https://github.com/mattjesc/energy-efficient-spi-sensor-network

Energy Efficient SPI (Serial Peripheral Interface) Sensor Network

fpga spi verilog vivado

Last synced: 18 Jan 2025

https://github.com/mattjesc/biomimetic-filtering-pwm-signal-smoothing

Biomimetic Filtering for PWM Signal Smoothing

asic biomimetics fpga pwm systemverilog verilog vhdl vivado vlsi

Last synced: 18 Jan 2025

https://github.com/mcleber/verilog_half_adder

Verilog half adder

half-adder verilog verilog-hdl

Last synced: 12 Jan 2025

https://github.com/qasimwani/karnaugh-map-batch-calculator

Calculates Multiple Karnaugh Maps at once using Selenium and custom built parser. The program then converts the Boolean Expressions into Dataflow Verilog (VHDL)

converts dataflow-verilog karnaugh-map karnaugh-map-solver karnaugh-maps selenium verilog web-scraping

Last synced: 27 Dec 2024

https://github.com/seyed0123/vendor

A vending machine system

verilog

Last synced: 24 Jan 2025

https://github.com/rejunity/atari-2600-fpga

Continue development of Atari 2600 in Verilog. Based on the original work by Daniel Beer.

atari-2600 atari2600 fpga retrogaming verilog

Last synced: 24 Jan 2025

https://github.com/anthonyhuang19/fpga-embedded-systems

This project focuses on designing digital circuits and microprocessors using FPGA, covering topics like Boolean logic, combinational circuits, state machines, CPU design, and memory structures (ROM/RAM).

fpga stata verilog

Last synced: 19 Jan 2025

https://github.com/lovc21/vhdl-code-from-lab

This repository includes VHDL code for laboratory projects conducted in an Integrated Circuits and Design course. It particularly emphasizes the 'Generator Tonov Jakob' project, which has been enhanced to showcase varying frequencies and tones. For detailed insights into these projects, refer to the course website.

verilog vhdl vhdl-code

Last synced: 19 Jan 2025

https://github.com/mc256/eecs2021

DO NOT COPY. MAKE SURE U UNDERSTAND.

eecs2021 mips verilog yorkuniversity

Last synced: 24 Jan 2025

https://github.com/28ritu/alu

An ALU Design in Verilog

alu verilog waveform

Last synced: 14 Feb 2025

https://github.com/yasnakateb/threshold

🖼✏️ My first baby steps into the world of image processing

grayscale image-processing threshold verilog verilog-hdl xilinx-ise

Last synced: 20 Jan 2025

https://github.com/elifgokpinar/microprocessor-design

Quartus Project

microprocessor quartus verilog

Last synced: 13 Jan 2025

https://github.com/kaushalmodi/nim-svvpi

Wrapper for SystemVerilog VPI headers sv_vpi_user.h and vpi_user.h

1364-2005 1800-2017 nim pli systemverilog verilog vpi

Last synced: 16 Jan 2025

https://github.com/yasnakateb/blinky

💡A Quartus II project testing the functionality of the Altera Cyclone IV EP4CE6E22C8N board

altera-fpga fpga verilog verilog-hdl

Last synced: 20 Jan 2025

https://github.com/mssola/hdl

Playing around with Hardware Description Languages.

hdl systemverilog verilog

Last synced: 27 Jan 2025

https://github.com/memgonzales/hdl-flip-flop

Compilation of Verilog behavioral models and test benches for the four types of flip-flops (SR, JK, D, and T)

behavioral-modeling computer-architecture flip-flop sequential-circuits verilog

Last synced: 20 Jan 2025

https://github.com/yappy2000d/fpga-make-win

Use the make tool to automate your work in CLI.

makefile quartus verilog

Last synced: 25 Jan 2025

https://github.com/princeranjan03/imageencryption_i-chip

This project focuses on creating a hardware-based encryption and decryption system that implements the Data Encryption Standard (DES) algorithm.

cipher cryptography data-encryption data-encryption-standard encoding encryption-decryption fpga image image-processing opencv rtldesign source-coding verilog verilog-hdl verilog-project vivado xilinx xilinx-vivado

Last synced: 31 Jan 2025

https://github.com/1sand0s/ssp-master-and-slave-verilog-module

FSM based SPI/SSP Master and Slave Verilog Module

fifo-buffer rtl verilog verilog-hdl

Last synced: 08 Feb 2025

https://github.com/dpieve/university

A resource for students learning programming and personal reference.

assembly cpp haskell haskell-exercises java matlab prolog python shell unifei-university verilog

Last synced: 14 Feb 2025

https://github.com/davoodeh/verilog2hspice

Do some simple conversions on Verilog files to make them compatible with HSpice

converter hdl hspice verilog

Last synced: 08 Feb 2025

https://github.com/birdybro/nand2tetris_mister

Nand2Tetris for MiSTer (as a learning experience for me).

hdl mister misterfpga tetris verilog verilog-hdl

Last synced: 01 Feb 2025

https://github.com/akielaries/hwverif

Sandbox for exploring Hardware Verification

verilog

Last synced: 20 Jan 2025

https://github.com/justin-marian/tiny-risc-v

Minimalist RISC-V with a five-stage pipeline. It serves as a platform for understanding processor design principles.

isa-architecture risc-v-architecture verilog

Last synced: 27 Dec 2024

https://github.com/justin-marian/fsm-vending-machine

FSM vending machine, it dispenses products based on user input and provides change based on the money introduced.

fsm vending-machine-proplem verilog

Last synced: 27 Dec 2024

https://github.com/panxuc/xucpu

NSCSCC “龙芯杯” 2024 个人赛 LoongArch 赛道参赛作品

fpga loongarch nscscc verilog

Last synced: 01 Feb 2025

https://github.com/calint/zen-one

experimental retro 16 bit cpu written in verilog xilinx vivado intended for fpga cmod s7 from digilent

16-bit cmod-s7 cpu fpga iverilog verilog vintage vivado

Last synced: 10 Jan 2025

https://github.com/pseudoincorrect/verilog_labs

Verilog labs

c dsp soft-cpu verilog

Last synced: 09 Feb 2025

https://github.com/jminjares4/digital-system-2

Digital System 2 Lab

digital-design verilog

Last synced: 10 Jan 2025

https://github.com/tanmayv25/microprocessor-system-design

Contains the lab work of Microprocessor System Design. All the FPGA prototyping, Drivers and OS modules.

fpga-soc linux-kernel-module sensor-devices verilog xilinx-vivado

Last synced: 30 Dec 2024

https://github.com/kaleid-liner/fpga-tetris

Tetris based on Nexys4 DDR FPGA Board

fpga tetris verilog

Last synced: 16 Jan 2025

https://github.com/radinshahdaei/ce40223-dsd

Practical assignments and projects for "Digital Systems Design".

verilog

Last synced: 28 Jan 2025

https://github.com/sunzey/cpu_project

recording codes of CPU under mips ISA in lecture of computer organization

buaa buaa-co cpu learning verilog

Last synced: 16 Jan 2025

https://github.com/taffarel55/verilog

Documentação dos exemplos que fiz enquanto estudava a linguagem de descrição de hardware Verilog.

verilog verilog-examples verilog-hdl

Last synced: 09 Jan 2025

https://github.com/pawel2000pl/verilogleddriver

Led RGB driver written in verilog, implemented for Mimas A7 Mini FPGA Development Board

fpga led-controller led-driver pwm pwm-driver systemverilog verilog vivado

Last synced: 22 Jan 2025