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Verilog
Verilog is a widely-used hardware description language (HDL) that enables designers to model, simulate, and synthesize digital circuits. It provides a text-based format for specifying the structure and behavior of electronic systems, making it easier to design complex hardware components such as microprocessors, memory, and communication devices.
- GitHub: https://github.com/topics/verilog
- Wikipedia: https://en.wikipedia.org/wiki/Verilog
- Aliases: hdl, hardware-description-language,
- Last updated: 2025-01-03 00:25:13 UTC
- JSON Representation
https://github.com/logisim-evolution/logisim-evolution
Digital logic design tool and simulator
circuit circuits digital-circuit digital-circuits digital-logic digital-logic-design education fpga logic logisim logisim-evolution simulator timing-diagram verilog vhdl
Last synced: 31 Dec 2024
https://github.com/chipsalliance/chisel3
Chisel: A Modern Hardware Design Language
chip-generator chisel chisel3 firrtl rtl scala verilog
Last synced: 09 Nov 2024
https://github.com/chipsalliance/chisel
Chisel: A Modern Hardware Design Language
chip-generator chisel chisel3 firrtl rtl scala verilog
Last synced: 31 Dec 2024
https://github.com/SI-RISCV/e200_opensource
Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
china core cpu nuclei risc-v ultra-low-power verilog
Last synced: 10 Nov 2024
https://github.com/verilator/verilator
Verilator open-source SystemVerilog simulator and lint system
compilers cpp rtl system-verilog systemc verilator verilog verilog-simulator
Last synced: 30 Oct 2024
https://github.com/jbush001/nyuziprocessor
GPGPU microprocessor architecture
fpga gpu gpu-computing graphics hardware microprocessor processor-architecture verilog
Last synced: 27 Dec 2024
https://github.com/jbush001/NyuziProcessor
GPGPU microprocessor architecture
fpga gpu gpu-computing graphics hardware microprocessor processor-architecture verilog
Last synced: 25 Oct 2024
https://github.com/cocotb/cocotb
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
python test uvm verification verilog vhdl
Last synced: 31 Dec 2024
https://github.com/fpgawars/icestudio
:snowflake: Visual editor for open FPGA boards
blocks editor fpga icestorm icestudio ide javascript lattice verilog
Last synced: 02 Jan 2025
https://github.com/FPGAwars/icestudio
:snowflake: Visual editor for open FPGA boards
blocks editor fpga icestorm icestudio ide javascript lattice verilog
Last synced: 01 Nov 2024
https://github.com/the-openroad-project/openroad
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
cpp def eda gdsii lef opendb-database openroad rtl tcl timing-analysis verilog
Last synced: 02 Jan 2025
https://github.com/pConst/basic_verilog
Must-have verilog systemverilog modules
altera debounce delay encoder fifo fpga hls pwm spi-interface spi-master synchronizer tcl uart uart-controller uart-protocol uart-receiver uart-tx uart-verilog verilog xilinx
Last synced: 25 Oct 2024
https://github.com/pconst/basic_verilog
Must-have verilog systemverilog modules
altera debounce delay encoder fifo fpga hls pwm spi-interface spi-master synchronizer tcl uart uart-controller uart-protocol uart-receiver uart-tx uart-verilog verilog xilinx
Last synced: 04 Dec 2024
https://github.com/The-OpenROAD-Project/OpenROAD
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
cpp def eda gdsii lef opendb-database openroad rtl tcl timing-analysis verilog
Last synced: 17 Nov 2024
https://github.com/analogdevicesinc/hdl
HDL libraries and projects
analog-devices fpga hacktoberfest hdl jesd204b verilog
Last synced: 04 Dec 2024
https://github.com/clash-lang/clash-compiler
Haskell to VHDL/Verilog/SystemVerilog compiler
asic fpga hardware-description-language haskell systemverilog verilog vhdl
Last synced: 02 Jan 2025
https://github.com/stnolting/neorv32
:rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
asic asip cpu embedded fpga gdb microcontroller neorv32 openocd processor risc-v riscv rtl rv32 safety soc soft-core system-on-chip verilog vhdl
Last synced: 27 Oct 2024
https://github.com/the-openroad-project/openlane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
130nm asic caravel foundry klayout magic netgen openram openroad rtl rtl2gds skywater soc-design system-on-chip verilog vlsi yosys
Last synced: 02 Jan 2025
https://github.com/The-OpenROAD-Project/OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
130nm asic caravel foundry klayout magic netgen openram openroad rtl rtl2gds skywater soc-design system-on-chip verilog vlsi yosys
Last synced: 09 Nov 2024
https://github.com/ZipCPU/zipcpu
A small, light weight, RISC CPU soft core
cpu cross-compiler fpga risc-cpu soft-core verilator verilog wishbone wishbone-bus zipcpu
Last synced: 25 Oct 2024
https://github.com/ultraembedded/riscv
RISC-V CPU Core (RV32IM)
asic cpu fpga pipeline-processor risc-v riscv-linux rv32i rv32im verification verilator verilog
Last synced: 29 Nov 2024
https://github.com/olofk/fusesoc
Package manager and build abstraction tool for FPGA/ASIC development
eda fpga package-manager python reuse verilog vhdl
Last synced: 01 Jan 2025
https://github.com/platformio/platformio-vscode-ide
PlatformIO IDE for VSCode: The next generation integrated development environment for IoT
debugger embedded fpga hardware iot microcontroller platformio verilog vscode
Last synced: 27 Dec 2024
https://google.github.io/xls/
XLS: Accelerated HW Synthesis
compiler high-level-synthesis hls mid-level-synthesis open-source pipeline verilog
Last synced: 15 Nov 2024
https://github.com/google/xls
XLS: Accelerated HW Synthesis
compiler high-level-synthesis hls mid-level-synthesis open-source pipeline verilog
Last synced: 02 Jan 2025
https://github.com/aappleby/metroboy
A repository of gate-level simulators and tools for the original Game Boy.
emulator gameboy gameboy-emulator hdl simulator verilog
Last synced: 27 Dec 2024
https://github.com/ultraembedded/biriscv
32-bit Superscalar RISC-V CPU
artix-7 asic branch-prediction coremark cpu fpga in-order linux pipelined-processors risc-v riscv-linux rv32i rv32im superscalar verilator verilog xilinx
Last synced: 27 Dec 2024
https://github.com/circuitvalley/usb_c_industrial_camera_fpga_usb3
Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.
camera csi fpga mipi mipi-csi-receiver usb usb3 uvc verilog
Last synced: 28 Dec 2024
https://github.com/hughperkins/verigpu
OpenSource GPU, in Verilog, loosely based on RISC-V ISA
asic-design gpu gpu-acceleration hardware-designs machine-learning risc-v risc-v-assembly verification verilog
Last synced: 12 Dec 2024
https://github.com/circuitvalley/USB_C_Industrial_Camera_FPGA_USB3
Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.
camera csi fpga mipi mipi-csi-receiver usb usb3 uvc verilog
Last synced: 03 Nov 2024
https://github.com/Redcrafter/verilog2factorio
This project will compile verilog (a hardware description language) into factorio blueprints.
Last synced: 19 Nov 2024
https://github.com/hughperkins/VeriGPU
OpenSource GPU, in Verilog, loosely based on RISC-V ISA
asic-design gpu gpu-acceleration hardware-designs machine-learning risc-v risc-v-assembly verification verilog
Last synced: 03 Nov 2024
https://github.com/ultraembedded/cores
Various HDL (Verilog) IP Cores
asic audio fpga i2s rtl sdram spi sram uart usb verilator verilog verilog-components verilog-hdl
Last synced: 12 Nov 2024
https://github.com/olofk/edalize
An abstraction library for interfacing EDA tools
altera eda fossi fpga ghdl icarus-verilog icestorm lattice modelsim riviera-pro simulation spyglass synthesis systemverilog verilator verilog vhdl vivado xilinx yosys
Last synced: 02 Jan 2025
https://github.com/princetonuniversity/openpiton
The OpenPiton Platform
fpga processor python research-platform verilog
Last synced: 27 Dec 2024
https://github.com/rejunity/z80-open-silicon
Z80 open-source silicon clone. Goal is to become a silicon proven, pin compatible, open-source replacement for classic Z80.
chip cpu foss retrocomputing tapeout tinytapeout verilog z80
Last synced: 24 Nov 2024
https://github.com/projf/projf-explore
Project F brings FPGAs to life with exciting open-source designs you can build on.
fpga graphics-hardware oshw verilog
Last synced: 09 Nov 2024
https://github.com/seldridge/verilog
Repository for basic (and not so basic) Verilog blocks with high re-use potential
Last synced: 07 Dec 2024
https://github.com/MikePopoloski/slang
SystemVerilog compiler and language services
compiler language-service parse slang systemverilog verilog
Last synced: 09 Nov 2024
https://github.com/OpenTimer/OpenTimer
A High-performance Timing Analysis Tool for VLSI Systems
cad circuit-analysis circuit-simulation circuit-simulator computer-aided-design cpp17 eda electronic-design-automation parallel-computing sta static-timing-analysis verilog vlsi vlsi-circuits vlsi-physical-design
Last synced: 25 Oct 2024
https://github.com/WangXuan95/FPGA-USB-Device
An FPGA-based USB full-speed device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB full-speed device端控制器，可实现USB串口、USB摄像头、USB音频、U盘、USB键盘等设备，只需要3个FPGA普通IO，而不需要额外的接口芯片。
cdc fpga keyboard rtl usb usb-audio usb-camera usb-cdc usb-controller usb-device usb-disk usb-hid usb-keyboard usb-microphone usb-serial usb-speaker usb-uart usb-uvc uvc verilog
Last synced: 10 Nov 2024
https://github.com/veryl-lang/veryl
Veryl: A Modern Hardware Description Language
rtl rust systemverilog verilog
Last synced: 31 Dec 2024
https://github.com/TerosTechnology/vscode-terosHDL
VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
fpga systemverilog verilog vhdl
Last synced: 09 Nov 2024
https://github.com/openrisc/mor1kx
mor1kx - an OpenRISC 1000 processor IP core
Last synced: 10 Nov 2024
https://github.com/WangXuan95/BSV_Tutorial_cn
一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。
bluespec bluespec-systemverilog bsv fpga hardware-description-language hdl verilog
Last synced: 09 Nov 2024
https://github.com/sudhamshu091/32-Verilog-Mini-Projects
Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 754 Addition Subtraction, Floating Point IEEE 754 Division, Floating Point IEEE 754 Multiplication, Fraction Multiplier, High Radix Multiplier, I2C and SPI Protocols, LFSR and CFSR, Logarithm Implementation, Mealy and Moore State Machine Implementation of Sequence Detector, Modified Booth Algorithm, Pipelined Multiplier, Restoring and Non Restoring Division, Sequential Multiplier, Shift and Add Binary Multiplier, Traffic Light Controller, Universal_Shift_Register, BCD Adder, Dual Address RAM and Dual Address ROM
miniproject verilog verilog-hdl verilog-project
Last synced: 25 Oct 2024
https://github.com/dalance/svls
SystemVerilog language server
language-server rust systemverilog verilog
Last synced: 09 Nov 2024
https://github.com/zachjs/sv2v
SystemVerilog to Verilog conversion
conversion systemverilog verilog yosys
Last synced: 26 Oct 2024
https://github.com/jks-prv/Beagle_SDR_GPS
KiwiSDR: BeagleBone web-accessible shortwave receiver and software-defined GPS
14-bit-adc beagle cape fpga gps hf open-source pcb sdr shortwave verilog vlf web-interface
Last synced: 03 Nov 2024
https://github.com/vmware-archive/cascade
A Just-In-Time Compiler for Verilog from VMware Research
fpga hardware jit just-in-time repl verilog
Last synced: 09 Nov 2024
https://github.com/t-k-233/risc-v-single-cycle-cpu
RISC-V 32bit single-cycle CPUs written in Logisim, Verilog, and Chisel
Last synced: 19 Dec 2024
https://github.com/splinedrive/kianRiscV
KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, linux soc included, .
cpu cyclone10lp divider ecp5 fpga ice40 ice40hx1k icebreaker icefun icoboard linux linuxsoc multiplier pipelined qmtech-board riscv rv32im softcpu ulx3s verilog
Last synced: 09 Nov 2024
https://github.com/jofrfu/tinytpu
Implementation of a Tensor Processing Unit for embedded systems and the IoT.
assembly embedded-systems fpga fpga-accelerator hardware-acceleration hardware-architectures hardware-description-language hardware-designs internet-of-things iot ip-core linux tensor tensorflow tpu verilog vhdl vivado xilinx zynq
Last synced: 31 Dec 2024
https://github.com/dalance/sv-parser
SystemVerilog parser library fully compliant with IEEE 1800-2017
parser rust rust-crate systemverilog verilog
Last synced: 26 Oct 2024
https://github.com/chipsalliance/surelog
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
antlr antlr4-grammar elaboration linter parser parser-ast preprocessor python-api systemverilog uvm verilog vpi vpi-api vpi-standard
Last synced: 27 Dec 2024
https://github.com/chipsalliance/Surelog
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
antlr antlr4-grammar elaboration linter parser parser-ast preprocessor python-api systemverilog uvm verilog vpi vpi-api vpi-standard
Last synced: 09 Nov 2024
https://github.com/jhshi/openofdm
Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.
Last synced: 03 Nov 2024
https://github.com/pymtl/pymtl3
Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
cycle-level-modeling hardware-generation hdl multi-level-modeling open-source-eda open-source-hardware pymtl python rtl systemverilog verilog
Last synced: 09 Nov 2024
https://github.com/fabriziotappero/ip-cores
A huge collection of VHDL/Verilog open-source IP cores scraped from the web
Last synced: 09 Nov 2024
https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
def eda gdsii lef opendb-database openroad rtl tcl timing-analysis verilog
Last synced: 29 Nov 2024
https://github.com/the-openroad-project/openroad-flow-scripts
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
def eda gdsii lef opendb-database openroad rtl tcl timing-analysis verilog
Last synced: 09 Nov 2024
https://github.com/dalance/svlint
SystemVerilog linter
lint linter rust systemverilog verilog
Last synced: 09 Nov 2024
https://github.com/leiwang1999/zynq-nvdla
NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.
fpga nvdla verilog yolox-nano zynq
Last synced: 26 Nov 2024
https://github.com/LeiWang1999/ZYNQ-NVDLA
NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.
fpga nvdla verilog yolox-nano zynq
Last synced: 28 Oct 2024
https://github.com/chipsalliance/sv-tests
Test suite designed to check compliance with the SystemVerilog standard.
compliance-testing hdl rtl symbiflow systemverilog verilog
Last synced: 23 Dec 2024
https://github.com/mshr-h/vscode-verilog-hdl-support
HDL support for VS Code
bluespec-systemverilog ctags hacktoberfest icarus-verilog iverilog language-server-client modelsim svls systemverilog systemverilog-support verilator verilog verilog-hdl vivado vscode
Last synced: 28 Dec 2024
https://github.com/nukeykt/Nuked-MD-FPGA
Mega Drive/Genesis core written in Verilog
68000 emulation fpga genesis mega-drive megadrive reverse-engineering sega-genesis sega-megadrive verilog yamaha ym2612 ym3438 ym6045 ym6046 ym7101 z80
Last synced: 30 Nov 2024
https://github.com/nic30/hdlconvertor
Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
antrl4 fpga parser python systemverilog systemverilog-parser verilog verilog-parser vhdl vhdl-parser
Last synced: 27 Dec 2024
https://github.com/Nic30/hdlConvertor
Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
antrl4 fpga parser python systemverilog systemverilog-parser verilog verilog-parser vhdl vhdl-parser
Last synced: 26 Oct 2024
https://github.com/jes/scamp-cpu
A homebrew 16-bit CPU with a homebrew Unix-like-ish operating system.
16-bit 16-bit-cpu cpu electronics hardware verilog
Last synced: 22 Nov 2024
https://github.com/chipsalliance/f4pga-examples
Example designs showing different ways to use F4PGA toolchains.
conda-packages f4pga fpga fpga-designs litex symbiflow-toolchains verilog vexriscv
Last synced: 23 Dec 2024
https://github.com/ZipCPU/wbuart32
A simple, basic, formally verified UART controller
fpga serialport uart uart-verilog verilator verilog wishbone wishbone-bus
Last synced: 25 Oct 2024
https://github.com/veripool/verilog-mode
Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
emacs-lisp systemverilog verilog verilog-mode
Last synced: 09 Nov 2024
https://github.com/rggen/rggen
Code generation tool for configuration and status registers
amba apb asic axi csr eda fpga ral register-descriptions rtl soc systemverilog uvm uvm-ral-model uvm-register-model verilog vhdl wiki-documents wishbone-bus
Last synced: 26 Oct 2024
https://github.com/f4pga/f4pga-arch-defs
FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
architecture-definitions artix artix7 documentation fpga hdl ice40 kintex7 lattice primitives python sphinx symbiflow synthesis toolchain verilog verilog-simulations verilog-simulator vpr xilinx-fpga
Last synced: 09 Nov 2024
https://github.com/DegateCommunity/Degate
A modern and open-source cross-platform software for chips reverse engineering.
chips cpp cross-platform cybersecurity gui multi-platform reverse-engineering security security-tools verilog vhdl vlsi
Last synced: 18 Nov 2024
https://github.com/WangXuan95/FPGA-SDcard-Reader
An FPGA-based SD-card reader to read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器，可以从FAT16或FAT32格式的SD卡中读取文件。
file-system fpga rtl sd-card sdcard sdio systemverilog verilog
Last synced: 10 Nov 2024
https://github.com/HackerFoo/poprc
A Compiler for the Popr Language
compiler concatenative dependent-types functional high-level-synthesis language linear-logic logic-programming non-deterministic partial-evaluators popr popr-compiler supercompiler verilog
Last synced: 09 Nov 2024
https://github.com/dpretet/async_fifo
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
asic asic-design async cdc cross-clock-domain fifo fifo-cache fifo-queue fpga hdl icarus-verilog synthesis verification verilator verilog verilog-hdl
Last synced: 10 Nov 2024
https://github.com/junningwu/learning-nvdla-notes
NVDLA is an Open source DL/ML accelerator, which is very suitable for individuals or college students. This is the NOTES when I learn and try. Hope THIS PAGE may Helps you a bit. Contact Me:[email protected]
deep-learning fpga-soc linux-kernel nerual-network verilog
Last synced: 19 Dec 2024
