https://github.com/saifalomari99/fpga_projects_saifalomari

This Repository is to showcase Saif Alomari's FPGA projects. Includes 25 high-level FPGA projects in various HDLs.

fpga systemverilog verilog

Last synced: 28 Dec 2024

https://github.com/mc256/eecs2021

DO NOT COPY. MAKE SURE U UNDERSTAND.

eecs2021 mips verilog yorkuniversity

Last synced: 24 Nov 2024

https://github.com/fuwn/iverilog-test-bench

☀️ Icarus Verilog Test-bench Template

de10 icarus-verilog verilog

Last synced: 10 Dec 2024

https://github.com/shpegun60/open_std_fpga

This std libraries on fpga

fpga-std standard-library-fpga verilog

Last synced: 18 Jan 2025

https://github.com/andrejchoo/cpldctrum

ZX Spectrum clone on CPLD

cpld divmmc verilog zx-spectrum

Last synced: 11 Dec 2024

https://github.com/andrejchoo/avr_like_core_on_verilog

Soft core with support for the AVR8 instructions on verilog

avr soft-core verilog

Last synced: 11 Dec 2024

https://github.com/limpix31/tangmega138kpro-blink

fpga hardware-design hdl system-verilog verilog

Last synced: 07 Jan 2025

https://github.com/sofiavalos/verilog_ethernet_10g_mac

Bloques y bancos de pruebas MAC para Ethernet 10G.

ethernet mac verilog

Last synced: 12 Dec 2024

https://github.com/pseudoincorrect/verilog_labs

Verilog labs

c dsp soft-cpu verilog

Last synced: 16 Dec 2024

https://github.com/youseftareq33/digital_buildcombinationalcircuit_2

Using Verilog HDL on Quartus application build combinational circuit

combinational-circuit verilog

Last synced: 24 Dec 2024

https://github.com/caite21/cpu-core

16-bit CPU Core Design in Verilog

cpu verilog xilinx-vivado

Last synced: 22 Jan 2025

https://github.com/seojuncha/fromthetransistor-fork

geohot's fromthetransistor project. Create a repo on my own because of the contribution map!!

assembler assembly c compiler fromthetransistor python uart verilog

Last synced: 11 Dec 2024

https://github.com/carlkidcrypto/digital-systems-engineering

A repo for ECE 440 (Digital Systems Engineering) class projects

systemverilog verilog xilinx-vivado zynq

Last synced: 16 Dec 2024

https://github.com/rejunity/atari-2600-fpga

Continue development of Atari 2600 in Verilog. Based on the original work by Daniel Beer.

atari-2600 atari2600 fpga retrogaming verilog

Last synced: 24 Nov 2024

https://github.com/seyed0123/vendor

A vending machine system

verilog

Last synced: 24 Nov 2024

https://github.com/orcalinux/computer-organization-and-architecture

Verilog code examples and materials for Computer Organization.

8086-microprocessor computer-architecture computer-organization modelsim pic programmable-interrupt-controller qu synthesis-project verilog

Last synced: 20 Dec 2024

https://github.com/mthszr/stopwatch-verilog

Projeto da 2ª unidade, para a disciplina de Sistemas Digitais, no qual consiste em desenvolver um Cronômetro Digital, utilizando Verilog com a base de Máquina de Estados Finitos.

verilog verilog-hdl

Last synced: 22 Jan 2025

https://github.com/skpro-glitch/resume

Find my resume, encapsulating my most prominent projects and experiences relevant for an entry level Hardware Engineering role. - Soham Kapur

algorithms-and-data-structures cadence cadence-virtuoso drone electronics-engineering java java-programming ltspice matlab soham-kapur sohamkapur team-aviators-international uav verilog verilog-hdl verilog-processor vit-chennai vit-university vitc vitchennai

Last synced: 12 Dec 2024

https://github.com/jjateen/snake-game-verilog

This repository showcases a Verilog-based Snake and Apple Game, developed for the ECL 106: Digital System Design with HDL course. Running on an Altera DE10-Lite FPGA board and displayed on a VGA monitor, players control a snake to collect apples while avoiding obstacles. The snake grows longer with each apple, making the game progressively harder.

altera-fpga de10-lite fpga quartus-prime verilog verilog-project

Last synced: 17 Jan 2025

https://github.com/abstractmachines/verilog-shift-register

A shift register in Verilog. Bidirectional pin use.

embedded-systems hardware shift-register verilog

Last synced: 12 Dec 2024

https://github.com/jminjares4/digital-system-2-template

Digital System 2 Template

digital-design verilog

Last synced: 10 Jan 2025

https://github.com/chili-chips-ba/uberclock

Digital systems are clocked. This project is about constructed a high-Q clock by simmering an ordinary quartz in a heavy numerical "secret sauce" that is fully open to the public.

clock-generator crystal dsp fpga risc-v rtl stratum-2 verilog

Last synced: 06 Dec 2024

https://github.com/mtaciano/fpgmips

Um processador baseado na arquitetura MIPS 32bits no FPGA DE2-115.

fpga mips processor verilog

Last synced: 12 Dec 2024

https://github.com/rehankarthikchandralal/implementation-of-a-configurable-neural-processing-unit-with-input-and-weight-stationary-dataflows

Used Verilog to design an entire NPU that supports two different kinds of dataflows to enable data reuse in order to reduce power consumption and resource utilization

neural-network-hardware verilog

Last synced: 17 Dec 2024

https://github.com/cepdnaclk/e18-co502-rv32im-pipeline-implementation-group4

Single-cycle MIPS-like processor with a memory subsystem including a cache.

computer-architecture risc-v verilog

Last synced: 11 Jan 2025

https://github.com/shuregg/riscv-simple-cpu

Creating a risc-v processor

cpu risc-v riscv riscv32 rtl systemverilog verification verilog verilog-hdl

Last synced: 13 Dec 2024

https://github.com/shuregg/fpga-practicum

learning about FPGA

fpga fpga-programming rtl systemverilog verilog vivado xilinx

Last synced: 13 Dec 2024

https://github.com/shuregg/miet-interfaces

Interfaces of computing systems

interfaces protocols verilog verilog-hdl

Last synced: 13 Dec 2024

https://github.com/mohammadmahdi-abdolhosseini/computer-architecture-lab

Computer Architecture Lab - Assignments - Fall 2023

arm-processor fpga modelsim quartus2 systemverilog verilog vhdl

Last synced: 07 Jan 2025

https://github.com/akafael/verilog-sandbox

selflearning tutorial-exercises verilog

Last synced: 29 Nov 2024

https://github.com/qasimwani/karnaugh-map-batch-calculator

Calculates Multiple Karnaugh Maps at once using Selenium and custom built parser. The program then converts the Boolean Expressions into Dataflow Verilog (VHDL)

converts dataflow-verilog karnaugh-map karnaugh-map-solver karnaugh-maps selenium verilog web-scraping

Last synced: 27 Dec 2024

https://github.com/samiyaalizaidi/fpga

Verilog implementation of the basic structure of an FPGA

digital-system-design fpga verilog vivado

Last synced: 16 Jan 2025

https://github.com/samiyaalizaidi/pipelined-risc-v-processor

A Pipelined RISC-V Processor with forwarding support and hazard detection.

assembly computer-architecture pipelining processor processor-architecture risc-v verilog vivado

Last synced: 16 Jan 2025

https://github.com/ewdlop/verilog-notes

HDLBit-Pratice. https://hdlbits.01xz.net/wiki/Main_Page

combinational-logic finte-state-machine flip-flops sequential-logic verilog

Last synced: 27 Dec 2024

https://github.com/ted-xie/icesuite

One-stop-shop for all the tools you need to get started with the iCE40 breakout board.

fpga ice40 lattice verilog yosys

Last synced: 12 Jan 2025

https://github.com/lasithaamarasinghe/uart-implementation-in-fpga

This is a group assignment done under semester 4 module EN2111:Electronic Circuit Design, .

fpga quartus-prime uart verilog

Last synced: 10 Jan 2025

https://github.com/bipinoli/vericlash

Implementation of bunch of circuits in Haskell (Clash) and Verilog to learn and compare them

clash-lang haskell verilog

Last synced: 21 Dec 2024

https://github.com/miku-218525/asic_lab

verilog

Last synced: 25 Dec 2024

https://github.com/ain1084/audio_level_meter

This is an audio level meter implemented using Verilog HDL.

audio machxo2 verilog visualization

Last synced: 20 Dec 2024

https://github.com/ain1084/machxo2_serial_to_spdif_transmitter

Serial (LPCM) to S/PDIF transmitter. Using MachXO2 (1200HC QFN32).

audio machxo2 spdif verilog

Last synced: 20 Dec 2024

https://github.com/elifgokpinar/microprocessor-design

Quartus Project

microprocessor quartus verilog

Last synced: 13 Jan 2025

https://github.com/shishir-dey/pcb-dev-fpga-ice40

A 2 layer development board with a Lattice Semiconductor ICE40UP5K-SG48ITR FPGA. Made with KiCad

development-board fpga hardware pcb-design verilog

Last synced: 14 Jan 2025

https://github.com/abdullahmaqbool22/arithmetic-logic-unit-alu

A final semester project for Digital Logic Data.

dld dld-project verilog

Last synced: 29 Dec 2024

https://github.com/yasnakateb/threshold

🖼✏️ My first baby steps into the world of image processing

grayscale image-processing threshold verilog verilog-hdl xilinx-ise

Last synced: 20 Jan 2025

https://github.com/ilovebacteria/elevator-state-machine

My Digital Logic course project - Elevator state machine

digital-logic moore-machine state-machine verilog

Last synced: 14 Nov 2024

https://github.com/mohammadmahdi-abdolhosseini/digital-logic-courses

Digital Systems 1 & 2 + Digital Systems Laboratory 1 + Digital Electronics Circuit +Microprocessor Based and Embedded Design courses projects

hspice systemverilog verilog

Last synced: 07 Jan 2025

https://github.com/3-o-3/cod5

Public Domain (⊄) Computer on FPGA

fpga fpga-soc public-domain ternary ternary-computer verilog

Last synced: 18 Dec 2024

https://github.com/dev-ritik/calculator

Xilinx college project

calculator college-project gui java-applet verilog xilinx

Last synced: 03 Dec 2024

https://github.com/woolseyworkshop/article-creating-a-configurable-multifunction-logic-gate-in-verilog

Creating A Configurable Multifunction Logic Gate In Verilog Article Resources

digital-logic verilog

Last synced: 29 Dec 2024

https://github.com/calint/znxcr

experimental retro 16 bit cpu written in verilog xilinx vivado intended for fpga Cmod S7 from Digilent

16-bit cmod-s7 cpu fpga verilog

Last synced: 10 Jan 2025

https://github.com/calint/tang-nano-9k--riscv

RISC-V rv32i implementation on Tang Nano 9K

risc-v rv32i tang-nano-9k verilog

Last synced: 10 Jan 2025

https://github.com/prinuvinod/digital-lab

These are some Verilog Programs

digital verilog

Last synced: 06 Jan 2025

https://github.com/calint/riscv

experiments implementing a risc-v cpu to gain experience with verilog and minimalistic cpu design

cmod-s7 cpu fpga iverilog risc-v riscv32i verilog vivado

Last synced: 10 Jan 2025

https://github.com/mattjesc/energy-efficient-spi-sensor-network

Energy Efficient SPI (Serial Peripheral Interface) Sensor Network

fpga spi verilog vivado

Last synced: 18 Jan 2025

https://github.com/ilyachichkov/verilog_labs_2023

Verilog & C Language practice

drivers fpga hardware low-level verilog

Last synced: 04 Jan 2025

https://github.com/mattjesc/biomimetic-filtering-pwm-signal-smoothing

Biomimetic Filtering for PWM Signal Smoothing

asic biomimetics fpga pwm systemverilog verilog vhdl vivado vlsi

Last synced: 18 Jan 2025

https://github.com/kaushalmodi/nim-svvpi

Wrapper for SystemVerilog VPI headers sv_vpi_user.h and vpi_user.h

1364-2005 1800-2017 nim pli systemverilog verilog vpi

Last synced: 16 Jan 2025

https://github.com/cepdnaclk/e18-co502-rv32im-pipeline-implementation-group03

RV32IM Pipeline Processor

risc-v verilog

Last synced: 11 Jan 2025

https://github.com/jminjares4/digital-system-2

Digital System 2 Lab

digital-design verilog

Last synced: 10 Jan 2025

https://github.com/tanmayv25/microprocessor-system-design

Contains the lab work of Microprocessor System Design. All the FPGA prototyping, Drivers and OS modules.

fpga-soc linux-kernel-module sensor-devices verilog xilinx-vivado

Last synced: 30 Dec 2024

https://github.com/mssola/hdl

Playing around with Hardware Description Languages.

hdl systemverilog verilog

Last synced: 29 Nov 2024

https://github.com/arefin994/bitstreamos

BitStreamOS --- A custom-designed MIPS CPU and operating system built from scratch. Features include a custom instruction set, assembler for converting assembly code to binary, CPU simulation with test benches, waveform visualization, and a basic OS implementation.

asm cpu mips-assembly os verilog

Last synced: 01 Jan 2025

https://github.com/kaleid-liner/fpga-tetris

Tetris based on Nexys4 DDR FPGA Board

fpga tetris verilog

Last synced: 16 Jan 2025

https://github.com/youseftareq33/digital_buildcombinationalcircuit_1

Using Verilog HDL on Quartus application build combinational circuit

combinational-circuit verilog

Last synced: 24 Dec 2024

https://github.com/cosminpopescu14/fpga

Sisteme FPGA

fpga verilog

Last synced: 25 Dec 2024

https://github.com/j-m-li/3o3

Ternary CPU for EPROM and FLASH memories

eprom public-domain verilog

Last synced: 06 Dec 2024

https://github.com/jackson-nestelroad/verilog-mips-processor

Single-cycle 32-bit MIPS processor implemented in SystemVerilog.

cpu mips processor verilog

Last synced: 01 Dec 2024

https://github.com/xigh/tinyfpga-counter

simple 1hz tinyfpga counter

fpga tinyfpga-bx verilog

Last synced: 08 Jan 2025

https://github.com/dibahk/verilog-language

A collection of verilog codes

gates verilog

Last synced: 08 Jan 2025

https://github.com/sunzey/cpu_project

recording codes of CPU under mips ISA in lecture of computer organization

buaa buaa-co cpu learning verilog

Last synced: 16 Jan 2025

https://github.com/memgonzales/hdl-flip-flop

Compilation of Verilog behavioral models and test benches for the four types of flip-flops (SR, JK, D, and T)

behavioral-modeling computer-architecture flip-flop sequential-circuits verilog

Last synced: 20 Jan 2025

https://github.com/taffarel55/verilog

Documentação dos exemplos que fiz enquanto estudava a linguagem de descrição de hardware Verilog.

verilog verilog-examples verilog-hdl

Last synced: 09 Jan 2025

https://github.com/camilaqpereira/oficina-verilog-siecomp

Neste repositórios estão disponibilizados todos os arquivos utilizados na Oficina Introdução ao Verilog Comportamental ministrado na XXXI SIECOMP (UEFS). Além disso, estão listados múltiplos recursos para estudo da linguagem.

oficina verilog verilog-code verilog-hdl

Last synced: 23 Jan 2025

https://github.com/rinminase/cpe512

verilog

Last synced: 27 Dec 2024

https://github.com/ranitmanik/cs-verilog-assignments

A collection of Verilog code snippets and assignments for computer science coursework.

assignment coding iverilog low-level-programming practice practice-programming verilog

Last synced: 30 Nov 2024

https://github.com/pawel2000pl/verilogleddriver

Led RGB driver written in verilog, implemented for Mimas A7 Mini FPGA Development Board

fpga led-controller led-driver pwm pwm-driver systemverilog verilog vivado

Last synced: 22 Jan 2025

https://github.com/mcleber/verilog_half_adder

Verilog half adder

half-adder verilog verilog-hdl

Last synced: 12 Jan 2025

https://github.com/birdybro/nand2tetris_mister

Nand2Tetris for MiSTer (as a learning experience for me).

hdl mister misterfpga tetris verilog verilog-hdl

Last synced: 05 Dec 2024

https://github.com/coldnew/nand2tetris

My notes and impement on Nand2Tetris courses

coursearea nand2tetris personal-notes verilator verilog

Last synced: 15 Jan 2025

https://github.com/eonu/fpga

Hardware implementations for basic digital circuit designs in Verilog with a Xilinx Artix-7 FPGA chip on a Digilent Basys 3 development board.

artix-7 basys3 circuits digital-design fpga hardware hardware-designs hdl simulation testbench verilog vivado

Last synced: 29 Dec 2024

https://github.com/ethanuppal/berkeley-hardfloat

Downstream hardfloat with custom patches

berkeley floating-point verilog

Last synced: 14 Dec 2024

https://github.com/davoodeh/verilog2hspice

Do some simple conversions on Verilog files to make them compatible with HSpice

converter hdl hspice verilog

Last synced: 15 Dec 2024

https://github.com/karagultm/datapath

The project involved extending the processor to support six new instructions: brv, jmxor, nori, blezal, jalpc, and baln. This required modifications to the control logic, the addition of new multiplexers, and the inclusion of status register flags to handle the specific behaviors of these instructions.

mips mips-architecture mips-assembly verilog

Last synced: 24 Dec 2024

https://github.com/harikrishnan669/verilog

KTU S4 DIGITAL LAB PROGRAMS (VERILOG)

cse ktu-s4-cse verilog

Last synced: 28 Nov 2024

https://github.com/niqzart/pylohd

High-level framework for simplification and systematization of processes in electronic design

converter hdl python thesis-project verilog

Last synced: 06 Dec 2024

https://github.com/kitune-san/kfmmc_v2

Multi media card access controller written in HDL

hdl mmc multimediacard sdc sdcard verilog verilog-hdl

Last synced: 21 Jan 2025

https://github.com/kitune-san/kf76489

KF76489 - 76489-like Digital Complex Sound generator written in SystemVerilog

fpga sn76489 systemverilog verilog

Last synced: 21 Jan 2025

https://github.com/lemongrb/digitaldesignwithverilog

Simple circuits designed with verilog

asic behavioural dataflow design digitalsystems fpga structural verilog verilog-code verilog-project verilogprojects

Last synced: 10 Jan 2025

https://github.com/kenny2github/verilog-cpu

A very rudimentary and haphazard CPU created in Verilog.

cpu verilog verilog-hdl

Last synced: 20 Dec 2024

https://github.com/calint/tang-nano-20k--riscv--cache-sdram

RISC-V implementation of rv32i for FPGA board Tang Nano 20K utilizing on-board burst SDRAM and flash

fpga risc-v rv32i systemverilog tang-nano-20k verilog

Last synced: 03 Jan 2025

https://github.com/akielaries/hwverif

Sandbox for exploring Hardware Verification

verilog

Last synced: 20 Jan 2025

https://github.com/andrejchoo/fpga_wav_player

A simple project for playing wav files on FPGA or CPLD

fpga spi-flash verilog wav

Last synced: 03 Jan 2025

https://github.com/rogerfan48/course-soph1-hdl

Materials and coursework for Hardware Design Lab (Sophomore Fall). Contains exercises, assignments, and laboratory work.

verilog vivado

Last synced: 08 Jan 2025

https://github.com/clementkim/logic-circuit-verilog

아주대학교 논리회로 - Verilog를 이용한 프로젝트 코드

logic-circuit verilog

Last synced: 15 Dec 2024

https://github.com/mosure/ece552-project-fall-2018

ece552 uw-madison verilog

Last synced: 29 Nov 2024

https://github.com/tdjsnelling/garbled-circuits

Yao’s Garbled Circuits in TypeScript

cryptography garbled-circuits javascript mpc multiparty-computation nodejs oblivious-transfer typescript verilog

Last synced: 15 Dec 2024

https://github.com/kayejd/nexysa7-fpga-programming

Embedded Programming Projects

embedded-systems fpga-programming verilog vivado

Last synced: 17 Jan 2025

https://github.com/mark-mdo47/fpga_rbg_2_rbgw

Lattice iCE40 FPGA convert WS2812b RGB from ESP32 to SK6812 RGBW

apio esp32-arduino fpga ice40 icestick led sk6812 verilog ws2812b

Last synced: 22 Jan 2025

https://github.com/kassane/fpga_course

Testing conducted during verilog studies

fpga verilog

Last synced: 13 Jan 2025

https://github.com/arsham-lh/logic-circuits

Simulation of logic circuits using Verilog, Proteus and other tools.

digital-circuits fsm logic-circuits mealy-machine moore-machine proteus verilog

Last synced: 17 Jan 2025