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Verilog

Verilog is a widely-used hardware description language (HDL) that enables designers to model, simulate, and synthesize digital circuits. It provides a text-based format for specifying the structure and behavior of electronic systems, making it easier to design complex hardware components such as microprocessors, memory, and communication devices.

GitHub: https://github.com/topics/verilog
Wikipedia: https://en.wikipedia.org/wiki/Verilog
Aliases: hdl, hardware-description-language,
Last updated: 2025-01-24 00:33:21 UTC
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https://github.com/andrejchoo/avr_like_core_on_verilog

Soft core with support for the AVR8 instructions on verilog

avr soft-core verilog

Last synced: 11 Dec 2024

https://github.com/mc256/eecs2021

DO NOT COPY. MAKE SURE U UNDERSTAND.

eecs2021 mips verilog yorkuniversity

Last synced: 24 Jan 2025

https://github.com/rainingcomputers/srp16

SRP16 is free and open ISA for 16-bit CPUs and Microcontrollers.

cpu instruction-set-architecture isa isa-specification microcontrollers open-embedded open-isa risc soft-core verilog

Last synced: 21 Dec 2024

https://github.com/pseudoincorrect/verilog_labs

Verilog labs

c dsp soft-cpu verilog

Last synced: 16 Dec 2024

https://github.com/shpegun60/open_std_fpga

This std libraries on fpga

fpga-std standard-library-fpga verilog

Last synced: 18 Jan 2025

https://github.com/limpix31/tangmega138kpro-blink

fpga hardware-design hdl system-verilog verilog

Last synced: 07 Jan 2025

https://github.com/seojuncha/fromthetransistor-fork

geohot's fromthetransistor project. Create a repo on my own because of the contribution map!!

assembler assembly c compiler fromthetransistor python uart verilog

Last synced: 11 Dec 2024

https://github.com/niw/chisel_test

A simple Chisel test project for myself to learn Chisel and FPGA.

chisel3 fpga orangecrab scala tinyfpga verilog

Last synced: 06 Jan 2025

https://github.com/tanuj-maheshwari/fpga

Configurable FPGA Fabric simulated in Verilog

fpga verilog

Last synced: 23 Jan 2025

https://github.com/carlkidcrypto/digital-systems-engineering

A repo for ECE 440 (Digital Systems Engineering) class projects

systemverilog verilog xilinx-vivado zynq

Last synced: 16 Dec 2024

https://github.com/bipinoli/vericlash

Implementation of bunch of circuits in Haskell (Clash) and Verilog to learn and compare them

clash-lang haskell verilog

Last synced: 21 Dec 2024

https://github.com/javiidiazglez/ec

Estructuras de Computadores

verilog

Last synced: 01 Jan 2025

https://github.com/skpro-glitch/resume

Find my resume, encapsulating my most prominent projects and experiences relevant for an entry level Hardware Engineering role. - Soham Kapur

algorithms-and-data-structures cadence cadence-virtuoso drone electronics-engineering java java-programming ltspice matlab soham-kapur sohamkapur team-aviators-international uav verilog verilog-hdl verilog-processor vit-chennai vit-university vitc vitchennai

Last synced: 12 Dec 2024

https://github.com/mongshil553/digital-engineering-verilog-assignments

Sophomore 2021 1st Semester Digital Engineering Verilog Assignments

fpga-programming verilog xilinx-vivado

Last synced: 13 Jan 2025

https://github.com/abstractmachines/verilog-shift-register

A shift register in Verilog. Bidirectional pin use.

embedded-systems hardware shift-register verilog

Last synced: 12 Dec 2024

https://github.com/jminjares4/digital-system-2-template

Digital System 2 Template

digital-design verilog

Last synced: 10 Jan 2025

https://github.com/urish/tt06-spell

A minimal, stack-based programming language created for The Skull CTF

tinytapeout verilog wizardry

Last synced: 11 Jan 2025

https://github.com/mtaciano/fpgmips

Um processador baseado na arquitetura MIPS 32bits no FPGA DE2-115.

fpga mips processor verilog

Last synced: 12 Dec 2024

https://github.com/rehankarthikchandralal/implementation-of-a-configurable-neural-processing-unit-with-input-and-weight-stationary-dataflows

Used Verilog to design an entire NPU that supports two different kinds of dataflows to enable data reuse in order to reduce power consumption and resource utilization

neural-network-hardware verilog

Last synced: 17 Dec 2024

https://github.com/mohamad-shosha/alu-verilog-proteus

This 4-bit ALU design project has been implemented as part of the [Computer Aided Design] in the university , where we applied Verilog for hardware design and Proteus for simulation.

proteus verilog

Last synced: 28 Dec 2024

https://github.com/shuregg/riscv-simple-cpu

Creating a risc-v processor

cpu risc-v riscv riscv32 rtl systemverilog verification verilog verilog-hdl

Last synced: 13 Dec 2024

https://github.com/shuregg/fpga-practicum

learning about FPGA

fpga fpga-programming rtl systemverilog verilog vivado xilinx

Last synced: 13 Dec 2024

https://github.com/shuregg/miet-interfaces

Interfaces of computing systems

interfaces protocols verilog verilog-hdl

Last synced: 13 Dec 2024

https://github.com/kaleid-liner/fpga-tetris

Tetris based on Nexys4 DDR FPGA Board

fpga tetris verilog

Last synced: 16 Jan 2025

https://github.com/harikrishnan669/verilog

KTU S4 DIGITAL LAB PROGRAMS (VERILOG)

cse ktu-s4-cse verilog

Last synced: 28 Nov 2024

https://github.com/rpigor/tpsim

TPSim (Timing and Power Simulator) is a gate-level circuit simulator with timing and power estimation capabilities

eda power-analysis simulator timing-analysis verilog

Last synced: 06 Jan 2025

https://github.com/abdullahmaqbool22/arithmetic-logic-unit-alu

A final semester project for Digital Logic Data.

dld dld-project verilog

Last synced: 29 Dec 2024

https://github.com/akielaries/hwverif

Sandbox for exploring Hardware Verification

verilog

Last synced: 20 Jan 2025

https://github.com/kitune-san/kf76489

KF76489 - 76489-like Digital Complex Sound generator written in SystemVerilog

fpga sn76489 systemverilog verilog

Last synced: 21 Jan 2025

https://github.com/lasithaamarasinghe/uart-implementation-in-fpga

This is a group assignment done under semester 4 module EN2111:Electronic Circuit Design, .

fpga quartus-prime uart verilog

Last synced: 10 Jan 2025

https://github.com/idorobots/upduino-blinky

Two simple Upduino projects that blink an RGB LED in various ways.

blinky fpga ice40 ice40up5k led upduino upduino-board verilog

Last synced: 20 Dec 2024

https://github.com/miku-218525/asic_lab

verilog

Last synced: 25 Dec 2024

https://github.com/justin-marian/tiny-risc-v

Minimalist RISC-V with a five-stage pipeline. It serves as a platform for understanding processor design principles.

isa-architecture risc-v-architecture verilog

Last synced: 27 Dec 2024

https://github.com/aledpl5/rock-paper-scissors-circuit

Uni project about the game rock-paper-scissors

blif circuit datapath datapath-design finate-state-machine sis systemverilog verilog

Last synced: 05 Jan 2025

https://github.com/ted-xie/icesuite

One-stop-shop for all the tools you need to get started with the iCE40 breakout board.

fpga ice40 lattice verilog yosys

Last synced: 12 Jan 2025

https://github.com/namberino/simple-uart

Simple UART implementation in FPGA

fpga uart verilog

Last synced: 20 Jan 2025

https://github.com/justin-marian/fsm-vending-machine

FSM vending machine, it dispenses products based on user input and provides change based on the money introduced.

fsm vending-machine-proplem verilog

Last synced: 27 Dec 2024

https://github.com/kitune-san/kfmmc_v2

Multi media card access controller written in HDL

hdl mmc multimediacard sdc sdcard verilog verilog-hdl

Last synced: 21 Jan 2025

https://github.com/mohammadmahdi-abdolhosseini/digital-logic-courses

Digital Systems 1 & 2 + Digital Systems Laboratory 1 + Digital Electronics Circuit +Microprocessor Based and Embedded Design courses projects

hspice systemverilog verilog

Last synced: 07 Jan 2025

https://github.com/shiro-raven/verilog-mips

A verilog-based MIPS processor with pipelining

assembly mips mips-architecture verilog

Last synced: 05 Dec 2024

https://github.com/3-o-3/cod5

Public Domain (⊄) Computer on FPGA

fpga fpga-soc public-domain ternary ternary-computer verilog

Last synced: 18 Dec 2024

https://github.com/ilyachichkov/verilog_labs_2023

Verilog & C Language practice

drivers fpga hardware low-level verilog

Last synced: 04 Jan 2025

https://github.com/mohammadmahdi-abdolhosseini/computer-architecture-lab

Computer Architecture Lab - Assignments - Fall 2023

arm-processor fpga modelsim quartus2 systemverilog verilog vhdl

Last synced: 07 Jan 2025

https://github.com/calint/znxcr

experimental retro 16 bit cpu written in verilog xilinx vivado intended for fpga Cmod S7 from Digilent

16-bit cmod-s7 cpu fpga verilog

Last synced: 10 Jan 2025

https://github.com/calint/tang-nano-9k--riscv

RISC-V rv32i implementation on Tang Nano 9K

risc-v rv32i tang-nano-9k verilog

Last synced: 10 Jan 2025

https://github.com/eonu/fpga

Hardware implementations for basic digital circuit designs in Verilog with a Xilinx Artix-7 FPGA chip on a Digilent Basys 3 development board.

artix-7 basys3 circuits digital-design fpga hardware hardware-designs hdl simulation testbench verilog vivado

Last synced: 29 Dec 2024

https://github.com/calint/riscv

experiments implementing a risc-v cpu to gain experience with verilog and minimalistic cpu design

cmod-s7 cpu fpga iverilog risc-v riscv32i verilog vivado

Last synced: 10 Jan 2025

https://github.com/ranitmanik/cs-verilog-assignments

A collection of Verilog code snippets and assignments for computer science coursework.

assignment coding iverilog low-level-programming practice practice-programming verilog

Last synced: 30 Nov 2024

https://github.com/mattjesc/energy-efficient-spi-sensor-network

Energy Efficient SPI (Serial Peripheral Interface) Sensor Network

fpga spi verilog vivado

Last synced: 18 Jan 2025

https://github.com/roscibely/arithmetic-logic-unit

A simple arithmetic logic unit (ALU) with System verilog

alu arithmetic verilog vhdl

Last synced: 21 Jan 2025

https://github.com/woolseyworkshop/article-getting-started-with-the-tinyfpga-bx

Getting Started With The TinyFPGA BX Article Resources

electronics programming tinyfpga-bx verilog

Last synced: 29 Dec 2024

https://github.com/mosure/ece552-project-fall-2018

ece552 uw-madison verilog

Last synced: 29 Nov 2024

https://github.com/woolseyworkshop/article-creating-a-configurable-multifunction-logic-gate-in-verilog

Creating A Configurable Multifunction Logic Gate In Verilog Article Resources

digital-logic verilog

Last synced: 29 Dec 2024

https://github.com/kassane/fpga_course

Testing conducted during verilog studies

fpga verilog

Last synced: 13 Jan 2025

https://github.com/mattjesc/biomimetic-filtering-pwm-signal-smoothing

Biomimetic Filtering for PWM Signal Smoothing

asic biomimetics fpga pwm systemverilog verilog vhdl vivado vlsi

Last synced: 18 Jan 2025

https://github.com/arefin994/bitstreamos

BitStreamOS --- A custom-designed MIPS CPU and operating system built from scratch. Features include a custom instruction set, assembler for converting assembly code to binary, CPU simulation with test benches, waveform visualization, and a basic OS implementation.

asm cpu mips-assembly os verilog

Last synced: 01 Jan 2025

https://github.com/caite21/cpu-core

16-bit CPU Core Design in Verilog

cpu verilog xilinx-vivado

Last synced: 22 Jan 2025

https://github.com/youseftareq33/digital_buildcombinationalcircuit_1

Using Verilog HDL on Quartus application build combinational circuit

combinational-circuit verilog

Last synced: 24 Dec 2024

https://github.com/cosminpopescu14/fpga

Sisteme FPGA

fpga verilog

Last synced: 25 Dec 2024

https://github.com/karagultm/datapath

The project involved extending the processor to support six new instructions: brv, jmxor, nori, blezal, jalpc, and baln. This required modifications to the control logic, the addition of new multiplexers, and the inclusion of status register flags to handle the specific behaviors of these instructions.

mips mips-architecture mips-assembly verilog

Last synced: 24 Dec 2024

https://github.com/youseftareq33/digital_buildcombinationalcircuit_2

Using Verilog HDL on Quartus application build combinational circuit

combinational-circuit verilog

Last synced: 24 Dec 2024

https://github.com/pawel2000pl/verilogleddriver

Led RGB driver written in verilog, implemented for Mimas A7 Mini FPGA Development Board

fpga led-controller led-driver pwm pwm-driver systemverilog verilog vivado

Last synced: 22 Jan 2025

https://github.com/tanmayv25/microprocessor-system-design

Contains the lab work of Microprocessor System Design. All the FPGA prototyping, Drivers and OS modules.

fpga-soc linux-kernel-module sensor-devices verilog xilinx-vivado

Last synced: 30 Dec 2024

https://github.com/mcleber/verilog_half_adder

Verilog half adder

half-adder verilog verilog-hdl

Last synced: 12 Jan 2025

https://github.com/peplxx/morse-coder

This project was made for optional fpga project during F23 Computer Architecture course. This is Quartus Project for turning fpga board into morse coder.

fpga-board fpga-programming morse-code quartus-prime verilog

Last synced: 20 Dec 2024

https://github.com/mthszr/stopwatch-verilog

Projeto da 2ª unidade, para a disciplina de Sistemas Digitais, no qual consiste em desenvolver um Cronômetro Digital, utilizando Verilog com a base de Máquina de Estados Finitos.

verilog verilog-hdl

Last synced: 22 Jan 2025

https://github.com/camilaqpereira/oficina-verilog-siecomp

Neste repositórios estão disponibilizados todos os arquivos utilizados na Oficina Introdução ao Verilog Comportamental ministrado na XXXI SIECOMP (UEFS). Além disso, estão listados múltiplos recursos para estudo da linguagem.

oficina verilog verilog-code verilog-hdl

Last synced: 23 Jan 2025

https://github.com/calint/zen-one

experimental retro 16 bit cpu written in verilog xilinx vivado intended for fpga cmod s7 from digilent

16-bit cmod-s7 cpu fpga iverilog verilog vintage vivado

Last synced: 10 Jan 2025

https://github.com/jjateen/snake-game-verilog

This repository showcases a Verilog-based Snake and Apple Game, developed for the ECL 106: Digital System Design with HDL course. Running on an Altera DE10-Lite FPGA board and displayed on a VGA monitor, players control a snake to collect apples while avoiding obstacles. The snake grows longer with each apple, making the game progressively harder.

altera-fpga de10-lite fpga quartus-prime verilog verilog-project

Last synced: 17 Jan 2025

https://github.com/taffarel55/verilog

Documentação dos exemplos que fiz enquanto estudava a linguagem de descrição de hardware Verilog.

verilog verilog-examples verilog-hdl

Last synced: 09 Jan 2025

https://github.com/strwdr/MaximatorZXSpectrum

ZX Spectrum implementation for maximator board

board fpga hdl max10 maximator nios soc verilog zx zx-spectrum

Last synced: 24 Oct 2024

https://github.com/samiyaalizaidi/fpga

Verilog implementation of the basic structure of an FPGA

digital-system-design fpga verilog vivado

Last synced: 16 Jan 2025

https://github.com/sunzey/cpu_project

recording codes of CPU under mips ISA in lecture of computer organization

buaa buaa-co cpu learning verilog

Last synced: 16 Jan 2025

https://github.com/samiyaalizaidi/pipelined-risc-v-processor

A Pipelined RISC-V Processor with forwarding support and hazard detection.

assembly computer-architecture pipelining processor processor-architecture risc-v verilog vivado

Last synced: 16 Jan 2025

https://github.com/qasimwani/karnaugh-map-batch-calculator

Calculates Multiple Karnaugh Maps at once using Selenium and custom built parser. The program then converts the Boolean Expressions into Dataflow Verilog (VHDL)

converts dataflow-verilog karnaugh-map karnaugh-map-solver karnaugh-maps selenium verilog web-scraping