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Verilog
Verilog is a widely-used hardware description language (HDL) that enables designers to model, simulate, and synthesize digital circuits. It provides a text-based format for specifying the structure and behavior of electronic systems, making it easier to design complex hardware components such as microprocessors, memory, and communication devices.
- GitHub: https://github.com/topics/verilog
- Wikipedia: https://en.wikipedia.org/wiki/Verilog
- Aliases: hdl, hardware-description-language,
- Last updated: 2025-01-03 00:25:13 UTC
- JSON Representation
https://github.com/avakar/usbcorev
A full-speed device-side USB peripheral core written in Verilog.
Last synced: 24 Dec 2024
https://github.com/ultraembedded/core_jpeg
High throughput JPEG decoder in Verilog for FPGA
axi-stream fpga jpeg-decoder mjpeg motion-jpeg verilog verilog-hdl
Last synced: 12 Nov 2024
https://github.com/nic30/hwt
VHDL/Verilog/SystemC code generator, simulator API written in python/c++
codegen codegenerator compiler fpga hcl hls rtl simulator systemc systemverilog uvm verilog vhdl
Last synced: 28 Dec 2024
https://github.com/Nic30/hwt
VHDL/Verilog/SystemC code generator, simulator API written in python/c++
codegen codegenerator compiler fpga hcl hls rtl simulator systemc systemverilog uvm verilog vhdl
Last synced: 26 Oct 2024
https://github.com/catkira/open5g_phy
A ressource efficient, customizable, synthesizable 5G NR lower PHY written in Verilog
5g 5g-nr 5g-simulation fpga hdl verilog
Last synced: 02 Jan 2025
https://github.com/hrvach/fpg1
FPGA implementation of DEC PDP-1 computer (1959) in Verilog, with CRT, Teletype and Console.
emulator fpga mister misterfpga pdp-1 retrocomputing verilog
Last synced: 28 Dec 2024
https://github.com/pwmarcz/fpga-chip8
CHIP-8 console on FPGA
chip-8 fpga tinyfpga-bx verilog
Last synced: 02 Nov 2024
https://github.com/fpgawars/fpga-peripherals
:seedling: :snowflake: Collection of open-source peripherals in Verilog
Last synced: 24 Dec 2024
https://github.com/FPGAwars/FPGA-peripherals
:seedling: :snowflake: Collection of open-source peripherals in Verilog
Last synced: 29 Nov 2024
https://github.com/risclite/R8051
8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.
Last synced: 28 Nov 2024
https://github.com/1801BM1/cpu11
Revengineered ancient PDP-11 CPUs, originals and clones
cpucore engineering hdl pdp-11 retrocomputing reverse verilog
Last synced: 30 Nov 2024
https://github.com/ZipCPU/vgasim
A Video display simulator
fpga gplv3 gtkmm verilator verilog vga video video-simulator
Last synced: 10 Nov 2024
https://github.com/aappleby/metron
A C++ to Verilog translation tool with some basic guarantees that your code will work.
c compiler cpp fpga hdl transpiler verilog
Last synced: 19 Dec 2024
https://github.com/tvlad1234/fakepga
Simulating Verilog designs on a microcontroller
fpga pico-sdk rp2040 simulator verilator verilog verilog-hdl
Last synced: 27 Dec 2024
https://github.com/1801BM1/vm80a
i8080 precise replica in Verilog, based on reverse engineering of real die
8080 cpucore fpga i8080a microprocessor retro retrocomputing reverse schematics verilog
Last synced: 29 Nov 2024
https://github.com/ulixxe/usb_cdc
Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs
asic bootloader cdc-acm fomu fpga serial tinyfpga-bx usb usb-cdc usb-device verilog
Last synced: 10 Nov 2024
https://github.com/ZipCPU/sdspi
SD-Card controller, using either SPI, SDIO, or eMMC interfaces
axi emmc fpga sd-card sd-interface sdio spi-interface verilator verilog verilog-components wishbone wishbone-bus
Last synced: 10 Nov 2024
https://github.com/zfturbo/mobilenet-in-fpga
Generator of verilog description for FPGA MobileNet implementation
Last synced: 22 Nov 2024
https://github.com/AUCOHL/Fault
A complete open-source design-for-testing (DFT) Solution
atpg dft eda fault-simulation jtag scan-chains stuck-at testing verilog verilog-hdl vlsi-cad
Last synced: 09 Nov 2024
https://github.com/alangarf/apple-one
An attempt at a small Verilog implementation of the original Apple 1 on an FPGA
apple apple1 ice40 ice40hx8k icoboard retrocomputing terasic-de0 tinyfpga upduino verilog
Last synced: 07 Dec 2024
https://github.com/liuqdev/8-bits-RISC-CPU-Verilog
Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。
Last synced: 28 Nov 2024
https://github.com/racerxdl/riskow
Learning how to make a RISC-V
fpga learning-exercise open-core opencore risc-v riskow verilog
Last synced: 26 Dec 2024
https://github.com/trinkle23897/mips32-cpu
奋战一学期，造台计算机（编译出的bit文件在release中，可以直接食用）
Last synced: 16 Dec 2024
https://github.com/Trinkle23897/mips32-cpu
奋战一学期，造台计算机（编译出的bit文件在release中，可以直接食用）
Last synced: 10 Nov 2024
https://github.com/AUCOHL/DFFRAM
Standard Cell Library based Memory Compiler using FF/Latch cells
asic-design electronics-design verilog vlsi vlsi-circuits vlsi-physical-design
Last synced: 17 Nov 2024
https://github.com/vivekmalneedi/veridian
A SystemVerilog Language Server
language-server lsp-server systemverilog verilog
Last synced: 09 Nov 2024
https://github.com/esonghori/tinygarble
TinyGarble: Logic Synthesis and Sequential Descriptions for Yao's Garbled Circuits
circuit-description garbled-circuits security-protocol verilog
Last synced: 10 Nov 2024
https://github.com/antonblanchard/vlsiffra
Create fast and efficient standard cell based adders, multipliers and multiply-adders.
adder amaranth-hdl booth dadda multiplier physical-design verilog vlsi
Last synced: 28 Nov 2024
https://github.com/jasonlin316/RISC-V-CPU
A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.
chip gate-level place-and-route processor risc-v riscv32 tape-out vector verilog
Last synced: 28 Nov 2024
https://github.com/rj45/rj32
A 16-bit RISC CPU with 32 instructions built with Digital for running on an FPGA.
cpu dvi fpga processor simulation simulator verilog vga
Last synced: 02 Jan 2025
https://github.com/microdynamics-cpu/tree-core-ide
:deciduous_tree: The next generation integrated development environment for processor design and verification. It has multi-hardware language support, open source IP management and easy-to-use rtl simulation toolset.
chisel3 ide processor riscv simualtion verilog vscode-extension waveform webgl
Last synced: 25 Oct 2024
https://github.com/ymherklotz/verismith
Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
Last synced: 01 Jan 2025
https://github.com/ultraembedded/openlogicbit
Open-source Logic Analyzer gateware for various FPGA dev boards/replacement gateware for commercially available logic analyzers.
altera-fpga digital-signal-analyzer fpga ftdi2232h ftdi232h lattice-fpga logic-analyzer verilog xilinx-fpga
Last synced: 12 Nov 2024
https://github.com/nxbyte/ARM-LEGv8
Verilog Implementation of an ARM LEGv8 CPU
arm arm-legv8-simulator forwarding-unit hazard-detection hennessy isa ldr legv8-arm multi-cycle patterson pipeline-cpu single-cycle verilog vivado xilinx
Last synced: 28 Nov 2024
https://github.com/tree-sitter/tree-sitter-verilog
SystemVerilog grammar for tree-sitter
grammar hacktoberfest parser tree-sitter verilog
Last synced: 27 Dec 2024
https://github.com/ultraembedded/riscv_soc
Basic RISC-V Test SoC
fpga-soc fpga-soc-linux linux risc-v riscv-linux system-on-chip systemc verilog
Last synced: 12 Nov 2024
https://github.com/SystemRDL/PeakRDL
Control and status register code generator toolchain
amba apb asic axi command-line-tool csr eda fpga hardware-description-language register-descriptions registers systemrdl-compiler systemverilog uvm uvm-register-model verilog
Last synced: 09 Nov 2024
https://github.com/ben-marshall/verilog-vcd-parser
A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.
parser simulation systemverilog trace vcd verilog vhdl
Last synced: 29 Nov 2024
https://github.com/jbush001/LispMicrocontroller
A microcontroller that natively executes a simple LISP dialect
cpu fpga hardware lisp microcontroller verilog
Last synced: 12 Nov 2024
https://github.com/jbush001/lispmicrocontroller
A microcontroller that natively executes a simple LISP dialect
cpu fpga hardware lisp microcontroller verilog
Last synced: 07 Nov 2024
https://github.com/AngeloJacobo/FPGA_Book_Experiments
My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu
Last synced: 07 Nov 2024
https://github.com/WilsonChen003/HDLGen
HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded functions, with ZERO learning-curve
asic automation hdl perl python rtl script soc verilog
Last synced: 26 Oct 2024
https://github.com/ultraembedded/core_ft60x_axi
FTDI FT600 SuperSpeed USB3.0 to AXI bus master
axi4 bus-master data-acquisition fpga ft600 ftdi-devices usb3 verilog xilinx-fpga
Last synced: 12 Nov 2024
https://github.com/OpenTimer/Parser-Verilog
A Standalone Structural Verilog Parser
bison-yacc circuit computer-aided-design cpp17 eda electronic-design-automation flex verilog vlsi-circuits vlsi-physical-design
Last synced: 29 Nov 2024
https://github.com/hsluoyz/atalanta
Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.
Last synced: 03 Jan 2025
https://github.com/risclite/ARM9-compatible-soft-CPU-core
This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone benchmark value: 1.2 DMIPS/MHz. It could be utilized in your FPGA design as one submodule, if you master the interface of this .v file. This IP core is very compact. It is one .v file and has only less 1800 lines.
Last synced: 28 Nov 2024
https://github.com/larsbrinkhoff/nybbleforth
Stack machine with 4-bit instructions
assembler cross-compiler forth fpga simulator stack-machine verilog virtual-machine
Last synced: 28 Oct 2024
https://github.com/princetonuniversity/autosva
AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made in the signal declaration section of an RTL module, generate liveness properties so that the module would eventually make forward progress.
design methodology-development rtl sva systemverilog verification verilog
Last synced: 20 Nov 2024
https://github.com/wyvernSemi/pcievhost
PCIe (1.0a to 2.0) Virtual host model for verilog
bfm c cosim modelling pcie pli verification verilog virtual
Last synced: 17 Nov 2024
https://github.com/ZipCPU/wbscope
A wishbone controlled scope for FPGA's
debugging-tools fpga verilator verilog wishbone wishbone-bus
Last synced: 10 Nov 2024
https://github.com/trcwm/speech256
An FPGA implementation of a classic 80ies speech synthesizer. Done for the Retro Challenge 2017/10.
fpga hdl retrochallenge speech synthesizer verilog
Last synced: 24 Dec 2024
https://github.com/hukenovs/intfftk
Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.
altera cooley-tukey-fft digital-signal-processing dsp fast-convolutions fast-fourier-transform fft fpga integer-arithmetic radix-2 route-optimization verilog vhdl vivado xilinx
Last synced: 19 Nov 2024
https://github.com/adumont/hrm-cpu
Human Resource Machine - CPU Design #HRM
control-signals cpu data-path fpga fpgawars fsm hrm human-resource-machine logisim verilog
Last synced: 10 Nov 2024
https://github.com/PrincetonUniversity/AutoSVA
AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made in the signal declaration section of an RTL module, generate liveness properties so that the module would eventually make forward progress.
design methodology-development rtl sva systemverilog verification verilog
Last synced: 17 Nov 2024
https://github.com/ultraembedded/core_dvi_framebuffer
Minimal DVI / HDMI Framebuffer
axi4 dvi fpga framebuffer hdmi verilog video xilinx-fpga
Last synced: 12 Nov 2024
https://github.com/mmicko/fpga101-workshop
FPGA 101 - Workshop materials
apio fpga hackaday icestorm icestudio micropython riscv verilog
Last synced: 08 Nov 2024
https://github.com/ultraembedded/core_usb_cdc
Basic USB-CDC device core (Verilog)
fpga usb usb-cdc usb-device verilog
Last synced: 12 Nov 2024
https://github.com/unixb0y/systemverilogsha256
SHA256 in (System-) Verilog / Open Source FPGA Miner
bitcoin fpga icarus-verilog mining sha256 systemverilog verilog
Last synced: 08 Nov 2024
https://github.com/ultraembedded/core_sdram_axi4
SDRAM controller with AXI4 interface
axi4 fpga sdram-controller verilog
Last synced: 12 Nov 2024
https://github.com/najaeda/naja
Structural Netlist API (and more) for EDA post synthesis flow development
asic cpp eda fpga netlist semiconductor verilog
Last synced: 17 Nov 2024
https://github.com/dpretet/svut
SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
flow foss gtkwave icarus-verilog mit-license python simulation simulator svut systemverilog tdd tdd-utilities testcase vcd verification-methodologies verilator verilog
Last synced: 09 Nov 2024
https://github.com/johnlon/spam-1
Home Brew 8 Bit CPU Hardware Implementation including a Verilog simulation, an assembler, a "C" Compiler and this repo also contains my research and learning. See also the Hackaday.IO project. https://hackaday.io/project/166922-spam-1-8-bit-cpu
8bit alu assembler cmos cpu design homebrew-cpu logism rom ttl verilog verilog-components vhdl
Last synced: 16 Nov 2024
https://github.com/cristian-mattarei/CoSA
CoreIR Symbolic Analyzer
formal-methods formal-verification hardware-verification model-checking satisfiability-modulo-theories systemverilog verilog
Last synced: 25 Oct 2024
https://github.com/mattvenn/vga-clock
Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.
Last synced: 15 Dec 2024
https://github.com/ljlin/MIPS48PipelineCPU
5 stage pipelined MIPS-32 processor
architecture cpu mips mips-architecture verilog
Last synced: 28 Nov 2024
https://github.com/SymbiFlow/sphinxcontrib-hdl-diagrams
Sphinx Extension which generates various types of diagrams from Verilog code.
diagrams documentation documentation-tool fpga hdl rtl sphinx sphinx-extension symbiflow verilog yosys
Last synced: 17 Nov 2024
https://github.com/Featherweight-IP/fwrisc
Featherweight RISC-V implementation
Last synced: 27 Oct 2024
https://github.com/ben-marshall/uart
A simple implementation of a UART modem in Verilog.
fpga hardware uart uart-verilog verilog verilog-hdl
Last synced: 29 Nov 2024
https://github.com/hukenovs/fp23fftk
Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL).
altera chirp convolution convolution-filter cooley-tukey-fft digital-signal-processing dsp fast-convolutions fast-fourier-transform fft floating-point fpga frequency-analysis ieee754 matlab octave radix-2 verilog vhdl xilinx
Last synced: 19 Nov 2024
https://github.com/jotego/jtopl
Verilog module compatible with Yamaha OPL chips
Last synced: 05 Dec 2024
https://github.com/racerxdl/lvds-7-to-1-serializer
An Verilog implementation of 7-to-1 LVDS Serializer. Which can be used for comunicating FPGAs with LVDS TFT Screens.
fpga lcd lvds screens serializer verilog
Last synced: 26 Dec 2024
https://github.com/ultraembedded/usb2sniffer
USB2Sniffer: High Speed USB 2.0 capture (for LambdaConcept USB2Sniffer hardware)
artix-7 fpga lambdaconcept-usb2sniffer-hardware rtl usb usb-analyzer usb-debugging usb-scanning usb-sniffer usb2 verilog wireshark xilinx-vivado
Last synced: 12 Nov 2024
https://github.com/sgherbst/svreal
Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
fixed-point floating-point icarus icarus-verilog irun iverilog ncsim simulation synthesis synthesizable systemverilog vcs verilator verilog vivado xcelium xrun
Last synced: 17 Nov 2024
https://github.com/brilliantlabsar/monocle-fpga
The FPGA application for Monocle's graphics, camera and microphone accelerators
Last synced: 10 Dec 2024
https://github.com/defparam/higan-verilog
This is a higan/Verilator co-simulation example/framework
emulation emulator fpga simulation snes snes-programming verilog verilog-hdl
Last synced: 24 Nov 2024
https://github.com/sam210723/fpga
Collection of projects for various FPGA development boards
5a-75b colorlight fpga hdl icestudio icesugar icesugar-nano mimas-v2 tinyfpga tinyfpga-bx verilog vga vga-driver
Last synced: 16 Nov 2024
https://github.com/Elphel/eddr3
mirror of https://git.elphel.com/Elphel/eddr3
ddr ddr3 fpga memory-controller open-core verilog xilinx zynq
Last synced: 29 Nov 2024
https://github.com/ghdl/docker
Scripts to build and use docker images including GHDL
actions ci dockerfiles ghdl gtkwave hardware icestorm nextpnr openocd pnr prjtrellis simulation synthesis testbench verilog vhdl vunit yosys
Last synced: 20 Dec 2024
https://github.com/stnolting/neorv32-verilog
♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
asic fpga ghdl icarus-verilog neorv32 verilog
Last synced: 10 Nov 2024
