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Verilog

Verilog is a widely-used hardware description language (HDL) that enables designers to model, simulate, and synthesize digital circuits. It provides a text-based format for specifying the structure and behavior of electronic systems, making it easier to design complex hardware components such as microprocessors, memory, and communication devices.

GitHub: https://github.com/topics/verilog
Wikipedia: https://en.wikipedia.org/wiki/Verilog
Aliases: hdl, hardware-description-language,
Last updated: 2025-02-08 00:27:45 UTC
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https://github.com/rithwikksvr/verilog-snake-game

Last semester we made a Snake Game implemented on Hardware. For this Purpose we used Basys 2 Spartan-3E FPGA, 7x5 LED Matrix and Verilog Programming.

fpga verilog

Last synced: 12 Jan 2025

https://github.com/amir78729/logical-circuits-course-final-project

My Logical Circuits course Final Project - Fall98(2019) - VERILOG

logical-circuits verilog

Last synced: 18 Jan 2025

https://github.com/eshansurendra/uart-fpga

This repository documents a project undertaken as part of the EN2111 Electronic Circuit Design module at the University of Moratuwa, focusing on the implementation of a UART communication link between two FPGA boards.

digital-design embedded-systems fpga quartus-prime systemverilog-hdl testbench uart verilog

Last synced: 18 Jan 2025

https://github.com/vgalovic/hdl_examples

A collection of VHDL and Verilog examples organized by language and practice section, with setup.tcl files for easy Vivado setup. These examples reflect my FPGA development practice and learning.

tcl verilog vhdl vivado

Last synced: 03 Jan 2025

https://github.com/ellisgl/driver-yl-3

Verilog code to run the YL-3 8 digit 7 segment display.

seven-segment verilog

Last synced: 19 Jan 2025

https://github.com/delhatch/flipdot_video

Video streaming from a camera to a 58x24 pixel flipdot display. See the two flipdot_display*.mp4 videos. All processing in Verilog RTL (no softcore uP).

altera de2-115 flipdot flipdots fpga verilog

Last synced: 13 Jan 2025

https://github.com/jamesits/verilog-basic-blocks

数电作业

verilog verilog-components xilinx-ise

Last synced: 01 Feb 2025

https://github.com/yasnakateb/sdramcontroller

🛠 A SDRAM controller in Verilog HDL

icarus-verilog iverilog memory-controller sdram sdram-controller verilog verilog-hdl

Last synced: 20 Jan 2025

https://github.com/mummanajagadeesh/i2c-protocol-verilog

Verilog Implementation of I2C Protocol using Finite State Machine (FSM) design

finite-state-machine fpga fsm i2c i2cprotocol verilog verilog-hdl verilog-project xilinx xilinx-vivado

Last synced: 25 Jan 2025

https://github.com/chayashri2308/parking_management

Parking Management System using Verilog, to identify the occupied and vacant space in a parking lot.

fpga verilog

Last synced: 31 Jan 2025

https://github.com/chayashri2308/vending_machine

A simple Vending Machine design for only one product using Verilog. The user can enter three different currency notes and based on the price of the product, the machine dispenses the product and gives the change.

verilog

Last synced: 31 Jan 2025

https://github.com/lorhansohaky/ufscar

Arquivos de atividades da UFSCar

arquitetura-de-computadores banco-de-dados c cap cgi compilador compiladores computacao-grafica cpp dc estruturas-de-dados grafos ori orientacao-a-objetos paa paradigmas sistemas-operacionais ufscar verilog

Last synced: 01 Feb 2025

https://github.com/m13253/sbmips

Naïve MIPS32-like CPU design with pipeline on a Xilinx FPGA

fpga mips mips32 verilog

Last synced: 01 Feb 2025

https://github.com/gatsbyz/processor-design-verilog

college stuff

assembly hardware verilog

Last synced: 01 Feb 2025

https://github.com/ghazaleze/microblaze-equation-solver

for solving cubic equation

c fpga verilog

Last synced: 05 Jan 2025

https://github.com/bucknalla/warc_fusesoc

WARC Open Fusesoc Cores Repository

hls ip migen open-cores verilog

Last synced: 09 Jan 2025

https://github.com/bucknalla/axis-interfacer

Extract AXI (Full, Lite and Stream) interfaces from Verilog source files

axi axi-lite axis verilog xilinx

Last synced: 09 Jan 2025

https://github.com/j-m-li/3o3

Ternary CPU for EPROM and FLASH memories

eprom public-domain verilog

Last synced: 01 Feb 2025

https://github.com/sofiavalos/verilog_ethernet_10g_mac

Bloques y bancos de pruebas MAC para Ethernet 10G.

ethernet mac verilog

Last synced: 06 Feb 2025

https://github.com/saifalomari99/fpga_projects_saifalomari

This Repository is to showcase Saif Alomari's FPGA projects. Includes 25 high-level FPGA projects in various HDLs.

fpga systemverilog verilog

Last synced: 28 Dec 2024

https://github.com/jackson-nestelroad/verilog-mips-processor

Single-cycle 32-bit MIPS processor implemented in SystemVerilog.

cpu mips processor verilog

Last synced: 29 Jan 2025

https://github.com/pseudoincorrect/verilog_labs

Verilog labs

c dsp soft-cpu verilog

Last synced: 16 Dec 2024

https://github.com/memgonzales/hdl-flip-flop

Compilation of Verilog behavioral models and test benches for the four types of flip-flops (SR, JK, D, and T)

behavioral-modeling computer-architecture flip-flop sequential-circuits verilog

Last synced: 20 Jan 2025

https://github.com/atoomnetmarc/fpga-playground

Random collection of FPGA related stuff.

apio fpga hdlbits ice40 ice40hx8k icestorm verilog yosys

Last synced: 03 Feb 2025

https://github.com/seojuncha/fromthetransistor-fork

geohot's fromthetransistor project with a little modification.

assembler assembly c compiler fromthetransistor python uart verilog

Last synced: 05 Feb 2025

https://github.com/andrejchoo/cpldctrum

ZX Spectrum clone on CPLD

cpld divmmc verilog zx-spectrum

Last synced: 05 Feb 2025

https://github.com/j-m-li/logical16x16

Hardware Description Language for EPROM and FLASH memories

eprom public-domain verilog

Last synced: 18 Nov 2024

https://github.com/niw/chisel_test

A simple Chisel test project for myself to learn Chisel and FPGA.

chisel3 fpga orangecrab scala tinyfpga verilog

Last synced: 06 Jan 2025

https://github.com/skpro-glitch/resume

Find my resume, encapsulating my most prominent projects and experiences relevant for an entry level Hardware Engineering role. - Soham Kapur

algorithms-and-data-structures cadence cadence-virtuoso drone electronics-engineering java java-programming ltspice matlab soham-kapur sohamkapur team-aviators-international uav verilog verilog-hdl verilog-processor vit-chennai vit-university vitc vitchennai

Last synced: 05 Feb 2025

https://github.com/jminjares4/digital-system-2-template

Digital System 2 Template

digital-design verilog

Last synced: 10 Jan 2025

https://github.com/woolseyworkshop/article-getting-started-with-the-tinyfpga-bx

Getting Started With The TinyFPGA BX Article Resources

electronics programming tinyfpga-bx verilog

Last synced: 29 Dec 2024

https://github.com/rehankarthikchandralal/implementation-of-a-configurable-neural-processing-unit-with-input-and-weight-stationary-dataflows

Used Verilog to design an entire NPU that supports two different kinds of dataflows to enable data reuse in order to reduce power consumption and resource utilization

neural-network-hardware verilog

Last synced: 17 Dec 2024

https://github.com/javiidiazglez/ec

Estructuras de Computadores

verilog

Last synced: 01 Jan 2025

https://github.com/mongshil553/digital-engineering-verilog-assignments

Sophomore 2021 1st Semester Digital Engineering Verilog Assignments

fpga-programming verilog xilinx-vivado

Last synced: 13 Jan 2025

https://github.com/urish/tt06-spell

A minimal, stack-based programming language created for The Skull CTF

tinytapeout verilog wizardry

Last synced: 11 Jan 2025

https://github.com/susiejojo/sobel_filter

Sobel filter for edge detection in images supporting parallel processing using Verilog on Xilinx ISE 13.4

hdl sobel-filter verilog xilinx-ise

Last synced: 17 Dec 2024

https://github.com/seyed0123/vendor

A vending machine system

verilog

Last synced: 24 Jan 2025

https://github.com/rejunity/atari-2600-fpga

Continue development of Atari 2600 in Verilog. Based on the original work by Daniel Beer.

atari-2600 atari2600 fpga retrogaming verilog

Last synced: 24 Jan 2025

https://github.com/lasithaamarasinghe/uart-implementation-in-fpga

This is a group assignment done under semester 4 module EN2111:Electronic Circuit Design, .

fpga quartus-prime uart verilog

Last synced: 10 Jan 2025

https://github.com/mohamad-shosha/alu-verilog-proteus

This 4-bit ALU design project has been implemented as part of the [Computer Aided Design] in the university , where we applied Verilog for hardware design and Proteus for simulation.

proteus verilog

Last synced: 28 Dec 2024

https://github.com/miku-218525/asic_lab

verilog

Last synced: 25 Dec 2024

https://github.com/sea-n/nctu-108b-dcd

108 Spring - Digital Circuit Design

homework nctu verilog

Last synced: 07 Jan 2025

https://github.com/tanmayv25/microprocessor-system-design

Contains the lab work of Microprocessor System Design. All the FPGA prototyping, Drivers and OS modules.

fpga-soc linux-kernel-module sensor-devices verilog xilinx-vivado

Last synced: 30 Dec 2024

https://github.com/rpigor/tpsim

TPSim (Timing and Power Simulator) is a gate-level circuit simulator with timing and power estimation capabilities

eda power-analysis simulator timing-analysis verilog

Last synced: 06 Jan 2025

https://github.com/anthonyhuang19/fpga-embedded-systems

This project focuses on designing digital circuits and microprocessors using FPGA, covering topics like Boolean logic, combinational circuits, state machines, CPU design, and memory structures (ROM/RAM).

fpga stata verilog

Last synced: 19 Jan 2025

https://github.com/dev-ritik/calculator

Xilinx college project

calculator college-project gui java-applet verilog xilinx

Last synced: 30 Jan 2025

https://github.com/lovc21/vhdl-code-from-lab

This repository includes VHDL code for laboratory projects conducted in an Integrated Circuits and Design course. It particularly emphasizes the 'Generator Tonov Jakob' project, which has been enhanced to showcase varying frequencies and tones. For detailed insights into these projects, refer to the course website.

verilog vhdl vhdl-code

Last synced: 19 Jan 2025

https://github.com/niqzart/pylohd

High-level framework for simplification and systematization of processes in electronic design

converter hdl python thesis-project verilog

Last synced: 01 Feb 2025

https://github.com/idorobots/upduino-blinky

Two simple Upduino projects that blink an RGB LED in various ways.

blinky fpga ice40 ice40up5k led upduino upduino-board verilog

Last synced: 20 Dec 2024

https://github.com/3-o-3/cod5

Public Domain (⊄) Computer on FPGA

fpga fpga-soc public-domain ternary ternary-computer verilog

Last synced: 18 Dec 2024

https://github.com/woolseyworkshop/article-creating-a-configurable-multifunction-logic-gate-in-verilog

Creating A Configurable Multifunction Logic Gate In Verilog Article Resources

digital-logic verilog

Last synced: 29 Dec 2024

https://github.com/mc256/eecs2021

DO NOT COPY. MAKE SURE U UNDERSTAND.

eecs2021 mips verilog yorkuniversity

Last synced: 24 Jan 2025

https://github.com/calint/znxcr

experimental retro 16 bit cpu written in verilog xilinx vivado intended for fpga Cmod S7 from Digilent

16-bit cmod-s7 cpu fpga verilog

Last synced: 10 Jan 2025

https://github.com/calint/tang-nano-9k--riscv

RISC-V rv32i implementation on Tang Nano 9K

risc-v rv32i tang-nano-9k verilog

Last synced: 10 Jan 2025

https://github.com/tanuj-maheshwari/fpga

Configurable FPGA Fabric simulated in Verilog

fpga verilog

Last synced: 23 Jan 2025

https://github.com/calint/riscv

experiments implementing a risc-v cpu to gain experience with verilog and minimalistic cpu design

cmod-s7 cpu fpga iverilog risc-v riscv32i verilog vivado

Last synced: 10 Jan 2025

https://github.com/shishir-dey/pcb-dev-fpga-ice40

A 2 layer development board with a Lattice Semiconductor ICE40UP5K-SG48ITR FPGA. Made with KiCad

development-board fpga hardware pcb-design verilog

Last synced: 14 Jan 2025

https://github.com/birdybro/nand2tetris_mister

Nand2Tetris for MiSTer (as a learning experience for me).

hdl mister misterfpga tetris verilog verilog-hdl

Last synced: 01 Feb 2025

https://github.com/yasnakateb/threshold

🖼✏️ My first baby steps into the world of image processing

grayscale image-processing threshold verilog verilog-hdl xilinx-ise

Last synced: 20 Jan 2025

https://github.com/aledpl5/rock-paper-scissors-circuit

Uni project about the game rock-paper-scissors

blif circuit datapath datapath-design finate-state-machine sis systemverilog verilog

Last synced: 05 Jan 2025

https://github.com/ilovebacteria/elevator-state-machine

My Digital Logic course project - Elevator state machine

digital-logic moore-machine state-machine verilog

Last synced: 14 Nov 2024

https://github.com/namberino/simple-uart

Simple UART implementation in FPGA

fpga uart verilog

Last synced: 20 Jan 2025

https://github.com/vlad-ivanov-name/verilog-zeroall

Resets all register to zero in a Verilog design

modelsim verilog

Last synced: 31 Jan 2025

https://github.com/karagultm/datapath

The project involved extending the processor to support six new instructions: brv, jmxor, nori, blezal, jalpc, and baln. This required modifications to the control logic, the addition of new multiplexers, and the inclusion of status register flags to handle the specific behaviors of these instructions.

mips mips-architecture mips-assembly verilog

Last synced: 24 Dec 2024

https://github.com/arefin994/bitstreamos

BitStreamOS --- A custom-designed MIPS CPU and operating system built from scratch. Features include a custom instruction set, assembler for converting assembly code to binary, CPU simulation with test benches, waveform visualization, and a basic OS implementation.

asm cpu mips-assembly os verilog

Last synced: 01 Jan 2025

https://github.com/youseftareq33/digital_buildcombinationalcircuit_2

Using Verilog HDL on Quartus application build combinational circuit

combinational-circuit verilog

Last synced: 24 Dec 2024

https://github.com/youseftareq33/digital_buildcombinationalcircuit_1

Using Verilog HDL on Quartus application build combinational circuit

combinational-circuit verilog

Last synced: 24 Dec 2024

https://github.com/cosminpopescu14/fpga

Sisteme FPGA

fpga verilog

Last synced: 25 Dec 2024

https://github.com/caite21/cpu-core

16-bit CPU Core Design in Verilog

cpu verilog xilinx-vivado

Last synced: 22 Jan 2025

https://github.com/kaleid-liner/fpga-tetris

Tetris based on Nexys4 DDR FPGA Board

fpga tetris verilog

Last synced: 16 Jan 2025

https://github.com/coldnew/nand2tetris

My notes and impement on Nand2Tetris courses

coursearea nand2tetris personal-notes verilator verilog

Last synced: 15 Jan 2025

https://github.com/dibahk/verilog-language

A collection of verilog codes

gates verilog

Last synced: 08 Jan 2025

https://github.com/wassimhedfi/fpga_adc_pwm_motorcontrol

This repository contains the implementation of a motor speed control system using an FPGA. The speed is adjusted dynamically through a potentiometer, leveraging ADC for analog-to-digital conversion and PWM for precise motor control.

adc de10-lite fpga html motor-speed pwm verilog vhdl

Last synced: 31 Jan 2025

https://github.com/mthszr/stopwatch-verilog

Projeto da 2ª unidade, para a disciplina de Sistemas Digitais, no qual consiste em desenvolver um Cronômetro Digital, utilizando Verilog com a base de Máquina de Estados Finitos.

verilog verilog-hdl

Last synced: 22 Jan 2025

https://github.com/camilaqpereira/oficina-verilog-siecomp

Neste repositórios estão disponibilizados todos os arquivos utilizados na Oficina Introdução ao Verilog Comportamental ministrado na XXXI SIECOMP (UEFS). Além disso, estão listados múltiplos recursos para estudo da linguagem.

oficina verilog verilog-code verilog-hdl

Last synced: 23 Jan 2025

https://github.com/kassane/fpga_course

Testing conducted during verilog studies

fpga verilog

Last synced: 13 Jan 2025

https://github.com/jjateen/snake-game-verilog

This repository showcases a Verilog-based Snake and Apple Game, developed for the ECL 106: Digital System Design with HDL course. Running on an Altera DE10-Lite FPGA board and displayed on a VGA monitor, players control a snake to collect apples while avoiding obstacles. The snake grows longer with each apple, making the game progressively harder.

altera-fpga de10-lite fpga quartus-prime verilog verilog-project

Last synced: 17 Jan 2025

https://github.com/davidvarshanidze/cpu

CPU implementation in MIPS Assembly and Verilog

cpu mips-assembly verilog

Last synced: 04 Feb 2025

https://github.com/yasnakateb/blinky

💡A Quartus II project testing the functionality of the Altera Cyclone IV EP4CE6E22C8N board

altera-fpga fpga verilog verilog-hdl

Last synced: 20 Jan 2025

https://github.com/peplxx/morse-coder

This project was made for optional fpga project during F23 Computer Architecture course. This is Quartus Project for turning fpga board into morse coder.

fpga-board fpga-programming morse-code quartus-prime verilog

Last synced: 20 Dec 2024

https://github.com/ewdlop/verilog-notes

HDLBit-Pratice. https://hdlbits.01xz.net/wiki/Main_Page

combinational-logic finte-state-machine flip-flops sequential-logic verilog

Last synced: 27 Dec 2024

https://github.com/rogerfan48/course-soph1-hdl

Materials and coursework for Hardware Design Lab (Sophomore Fall). Contains exercises, assignments, and laboratory work.

verilog vivado

Last synced: 08 Jan 2025

https://github.com/strwdr/MaximatorZXSpectrum

ZX Spectrum implementation for maximator board

board fpga hdl max10 maximator nios soc verilog zx zx-spectrum

Last synced: 24 Oct 2024

https://github.com/xigh/tinyfpga-counter

simple 1hz tinyfpga counter

fpga tinyfpga-bx verilog

Last synced: 08 Jan 2025

https://github.com/guntas-13/verilog

Compilation of all the Verilog Assignments in the course ES204 - Digital Systems (Spring 2024) - Prof. Joycee Mekie

verilog verilog-hdl

Last synced: 30 Jan 2025

https://github.com/guntas-13/mips-processor-basys3

Full FPGA Implementation of 32-bit FSM-based Multi-State MIPS Processor

mips-assembly mips-processor processor-architecture verilog

Last synced: 30 Jan 2025

https://github.com/azazhassankhan/verilogutilitysuite

VerilogUtilitySuite 🚀 Welcome to our SystemVerilog playground! 🤖 Dive into the world of hardware description language (HDL) with our repository, where RTL designs meet creativity.

circuit component-architecture systemverilog verilog

Last synced: 21 Jan 2025

https://github.com/radinshahdaei/ce40223-dsd

Practical assignments and projects for "Digital Systems Design".

verilog

Last synced: 28 Jan 2025

https://github.com/theoplayz2/eda-explorer

Инструмент на Python для разведочного анализа данных (EDA) и визуализации, поддерживающий загрузку данных CSV и JSON, с модульной архитектурой ООП. Практическая работа по теме: "Обнаружение и визуализация данных для понимания их сущности" дисциплины "МДК 13.01: Основы применения методов искусственного интеллекта в программировании".

analysis battery-life cqrs csharp data-analysis eeg-analysis exploratorydataanalysis json-visualization matplotlib messaging profile-report python verilog visualization