Ecosyste.ms: Awesome

An open API service indexing awesome lists of open source software.

Awesome Lists | Featured Topics | Projects

Verilog

Verilog is a widely-used hardware description language (HDL) that enables designers to model, simulate, and synthesize digital circuits. It provides a text-based format for specifying the structure and behavior of electronic systems, making it easier to design complex hardware components such as microprocessors, memory, and communication devices.

https://github.com/kaushalmodi/nim-svvpi

Wrapper for SystemVerilog VPI headers sv_vpi_user.h and vpi_user.h

1364-2005 1800-2017 nim pli systemverilog verilog vpi

Last synced: 16 Jan 2025

https://github.com/qasimwani/karnaugh-map-batch-calculator

Calculates Multiple Karnaugh Maps at once using Selenium and custom built parser. The program then converts the Boolean Expressions into Dataflow Verilog (VHDL)

converts dataflow-verilog karnaugh-map karnaugh-map-solver karnaugh-maps selenium verilog web-scraping

Last synced: 27 Dec 2024

https://github.com/strwdr/MaximatorZXSpectrum

ZX Spectrum implementation for maximator board

board fpga hdl max10 maximator nios soc verilog zx zx-spectrum

Last synced: 24 Oct 2024

https://github.com/peplxx/morse-coder

This project was made for optional fpga project during F23 Computer Architecture course. This is Quartus Project for turning fpga board into morse coder.

fpga-board fpga-programming morse-code quartus-prime verilog

Last synced: 20 Dec 2024

https://github.com/kassane/fpga_course

Testing conducted during verilog studies

fpga verilog

Last synced: 13 Jan 2025

https://github.com/namberino/simple-uart

Simple UART implementation in FPGA

fpga uart verilog

Last synced: 20 Jan 2025

https://github.com/idorobots/upduino-blinky

Two simple Upduino projects that blink an RGB LED in various ways.

blinky fpga ice40 ice40up5k led upduino upduino-board verilog

Last synced: 20 Dec 2024

https://github.com/rpigor/tpsim

TPSim (Timing and Power Simulator) is a gate-level circuit simulator with timing and power estimation capabilities

eda power-analysis simulator timing-analysis verilog

Last synced: 06 Jan 2025

https://github.com/mohamad-shosha/alu-verilog-proteus

This 4-bit ALU design project has been implemented as part of the [Computer Aided Design] in the university , where we applied Verilog for hardware design and Proteus for simulation.

proteus verilog

Last synced: 28 Dec 2024

https://github.com/urish/tt06-spell

A minimal, stack-based programming language created for The Skull CTF

tinytapeout verilog wizardry

Last synced: 11 Jan 2025

https://github.com/mongshil553/digital-engineering-verilog-assignments

Sophomore 2021 1st Semester Digital Engineering Verilog Assignments

fpga-programming verilog xilinx-vivado

Last synced: 13 Jan 2025

https://github.com/javiidiazglez/ec

Estructuras de Computadores

verilog

Last synced: 01 Jan 2025

https://github.com/niw/chisel_test

A simple Chisel test project for myself to learn Chisel and FPGA.

chisel3 fpga orangecrab scala tinyfpga verilog

Last synced: 06 Jan 2025

https://github.com/saifalomari99/fpga_projects_saifalomari

This Repository is to showcase Saif Alomari's FPGA projects. Includes 25 high-level FPGA projects in various HDLs.

fpga systemverilog verilog

Last synced: 28 Dec 2024

https://github.com/sofiavalos/verilog_ethernet_10g_mac

Bloques y bancos de pruebas MAC para Ethernet 10G.

ethernet mac verilog

Last synced: 12 Dec 2024

https://github.com/chili-chips-ba/uberclock

Digital systems are clocked. This project is about constructed a high-Q clock by simmering an ordinary quartz in a heavy numerical "secret sauce" that is fully open to the public.

clock-generator crystal dsp fpga risc-v rtl stratum-2 verilog

Last synced: 06 Dec 2024

https://github.com/cepdnaclk/e18-co502-rv32im-pipeline-implementation-group4

Single-cycle MIPS-like processor with a memory subsystem including a cache.

computer-architecture risc-v verilog

Last synced: 11 Jan 2025

https://github.com/ain1084/audio_level_meter

This is an audio level meter implemented using Verilog HDL.

audio machxo2 verilog visualization

Last synced: 20 Dec 2024

https://github.com/ain1084/machxo2_serial_to_spdif_transmitter

Serial (LPCM) to S/PDIF transmitter. Using MachXO2 (1200HC QFN32).

audio machxo2 spdif verilog

Last synced: 20 Dec 2024

https://github.com/prinuvinod/digital-lab

These are some Verilog Programs

digital verilog

Last synced: 06 Jan 2025

https://github.com/j-m-li/3o3

Ternary CPU for EPROM and FLASH memories

eprom public-domain verilog

Last synced: 06 Dec 2024

https://github.com/jackson-nestelroad/verilog-mips-processor

Single-cycle 32-bit MIPS processor implemented in SystemVerilog.

cpu mips processor verilog

Last synced: 01 Dec 2024

https://github.com/birdybro/nand2tetris_mister

Nand2Tetris for MiSTer (as a learning experience for me).

hdl mister misterfpga tetris verilog verilog-hdl

Last synced: 05 Dec 2024

https://github.com/ethanuppal/berkeley-hardfloat

Downstream hardfloat with custom patches

berkeley floating-point verilog

Last synced: 14 Dec 2024

https://github.com/niqzart/pylohd

High-level framework for simplification and systematization of processes in electronic design

converter hdl python thesis-project verilog

Last synced: 06 Dec 2024

https://github.com/kenny2github/verilog-cpu

A very rudimentary and haphazard CPU created in Verilog.

cpu verilog verilog-hdl

Last synced: 20 Dec 2024

https://github.com/risto97/socmake

Build system for RTL and SoC designs

cmake cpu hardware rtl simulation systemc systemonchip systemrdl verilog

Last synced: 21 Dec 2024

https://github.com/markmll/todaystart-a153

As-shipped demo for the Altera Cyclone TodayStart-A153 board. Requires Quartus-II 10.1 SP1 minimum.

fpga verilog vhdl

Last synced: 21 Dec 2024

https://github.com/rainingcomputers/srp16

SRP16 is free and open ISA for 16-bit CPUs and Microcontrollers.

cpu instruction-set-architecture isa isa-specification microcontrollers open-embedded open-isa risc soft-core verilog

Last synced: 21 Dec 2024

https://github.com/carlkidcrypto/digital-systems-engineering

A repo for ECE 440 (Digital Systems Engineering) class projects

systemverilog verilog xilinx-vivado zynq

Last synced: 16 Dec 2024

https://github.com/bipinoli/vericlash

Implementation of bunch of circuits in Haskell (Clash) and Verilog to learn and compare them

clash-lang haskell verilog

Last synced: 21 Dec 2024

https://github.com/abdullahmaqbool22/arithmetic-logic-unit-alu

A final semester project for Digital Logic Data.

dld dld-project verilog

Last synced: 29 Dec 2024

https://github.com/mohammadmahdi-abdolhosseini/digital-logic-courses

Digital Systems 1 & 2 + Digital Systems Laboratory 1 + Digital Electronics Circuit +Microprocessor Based and Embedded Design courses projects

hspice systemverilog verilog

Last synced: 07 Jan 2025

https://github.com/ilyachichkov/verilog_labs_2023

Verilog & C Language practice

drivers fpga hardware low-level verilog

Last synced: 04 Jan 2025

https://github.com/eonu/fpga

Hardware implementations for basic digital circuit designs in Verilog with a Xilinx Artix-7 FPGA chip on a Digilent Basys 3 development board.

artix-7 basys3 circuits digital-design fpga hardware hardware-designs hdl simulation testbench verilog vivado

Last synced: 29 Dec 2024

https://github.com/woolseyworkshop/article-getting-started-with-the-tinyfpga-bx

Getting Started With The TinyFPGA BX Article Resources

electronics programming tinyfpga-bx verilog

Last synced: 29 Dec 2024

https://github.com/woolseyworkshop/article-creating-a-configurable-multifunction-logic-gate-in-verilog

Creating A Configurable Multifunction Logic Gate In Verilog Article Resources

digital-logic verilog

Last synced: 29 Dec 2024

https://github.com/karagultm/datapath

The project involved extending the processor to support six new instructions: brv, jmxor, nori, blezal, jalpc, and baln. This required modifications to the control logic, the addition of new multiplexers, and the inclusion of status register flags to handle the specific behaviors of these instructions.

mips mips-architecture mips-assembly verilog

Last synced: 24 Dec 2024

https://github.com/youseftareq33/digital_buildcombinationalcircuit_2

Using Verilog HDL on Quartus application build combinational circuit

combinational-circuit verilog

Last synced: 24 Dec 2024

https://github.com/davoodeh/verilog2hspice

Do some simple conversions on Verilog files to make them compatible with HSpice

converter hdl hspice verilog

Last synced: 15 Dec 2024

https://github.com/dibahk/verilog-language

A collection of verilog codes

gates verilog

Last synced: 08 Jan 2025

https://github.com/xigh/tinyfpga-counter

simple 1hz tinyfpga counter

fpga tinyfpga-bx verilog

Last synced: 08 Jan 2025

https://github.com/azazhassankhan/verilogutilitysuite

VerilogUtilitySuite 🚀 Welcome to our SystemVerilog playground! 🤖 Dive into the world of hardware description language (HDL) with our repository, where RTL designs meet creativity.

circuit component-architecture systemverilog verilog

Last synced: 21 Jan 2025

https://github.com/kitune-san/kf76489

KF76489 - 76489-like Digital Complex Sound generator written in SystemVerilog

fpga sn76489 systemverilog verilog

Last synced: 21 Jan 2025

https://github.com/kitune-san/kfmmc_v2

Multi media card access controller written in HDL

hdl mmc multimediacard sdc sdcard verilog verilog-hdl

Last synced: 21 Jan 2025

https://github.com/roscibely/arithmetic-logic-unit

A simple arithmetic logic unit (ALU) with System verilog

alu arithmetic verilog vhdl

Last synced: 21 Jan 2025

https://github.com/sea-n/nctu-108b-dcd

108 Spring - Digital Circuit Design

homework nctu verilog

Last synced: 07 Jan 2025

https://github.com/rogerfan48/course-soph1-hdl

Materials and coursework for Hardware Design Lab (Sophomore Fall). Contains exercises, assignments, and laboratory work.

verilog vivado

Last synced: 08 Jan 2025

https://github.com/coldnew/nand2tetris

My notes and impement on Nand2Tetris courses

coursearea nand2tetris personal-notes verilator verilog

Last synced: 15 Jan 2025

https://github.com/pawel2000pl/verilogleddriver

Led RGB driver written in verilog, implemented for Mimas A7 Mini FPGA Development Board

fpga led-controller led-driver pwm pwm-driver systemverilog verilog vivado

Last synced: 22 Jan 2025

https://github.com/ranitmanik/cs-verilog-assignments

A collection of Verilog code snippets and assignments for computer science coursework.

assignment coding iverilog low-level-programming practice practice-programming verilog

Last synced: 30 Nov 2024

https://github.com/taffarel55/verilog

Documentação dos exemplos que fiz enquanto estudava a linguagem de descrição de hardware Verilog.

verilog verilog-examples verilog-hdl

Last synced: 09 Jan 2025

https://github.com/sunzey/cpu_project

recording codes of CPU under mips ISA in lecture of computer organization

buaa buaa-co cpu learning verilog

Last synced: 16 Jan 2025

https://github.com/kaleid-liner/fpga-tetris

Tetris based on Nexys4 DDR FPGA Board

fpga tetris verilog

Last synced: 16 Jan 2025

https://github.com/tanmayv25/microprocessor-system-design

Contains the lab work of Microprocessor System Design. All the FPGA prototyping, Drivers and OS modules.

fpga-soc linux-kernel-module sensor-devices verilog xilinx-vivado

Last synced: 30 Dec 2024

https://github.com/jminjares4/digital-system-2

Digital System 2 Lab

digital-design verilog

Last synced: 10 Jan 2025

https://github.com/ilovebacteria/elevator-state-machine

My Digital Logic course project - Elevator state machine

digital-logic moore-machine state-machine verilog

Last synced: 14 Nov 2024

https://github.com/shishir-dey/pcb-dev-fpga-ice40

A 2 layer development board with a Lattice Semiconductor ICE40UP5K-SG48ITR FPGA. Made with KiCad

development-board fpga hardware pcb-design verilog

Last synced: 14 Jan 2025

https://github.com/samiyaalizaidi/pipelined-risc-v-processor

A Pipelined RISC-V Processor with forwarding support and hazard detection.

assembly computer-architecture pipelining processor processor-architecture risc-v verilog vivado

Last synced: 16 Jan 2025

https://github.com/samiyaalizaidi/fpga

Verilog implementation of the basic structure of an FPGA

digital-system-design fpga verilog vivado

Last synced: 16 Jan 2025

https://github.com/jjateen/snake-game-verilog

This repository showcases a Verilog-based Snake and Apple Game, developed for the ECL 106: Digital System Design with HDL course. Running on an Altera DE10-Lite FPGA board and displayed on a VGA monitor, players control a snake to collect apples while avoiding obstacles. The snake grows longer with each apple, making the game progressively harder.

altera-fpga de10-lite fpga quartus-prime verilog verilog-project

Last synced: 17 Jan 2025

https://github.com/seyed0123/vendor

A vending machine system

verilog

Last synced: 24 Nov 2024

https://github.com/rejunity/atari-2600-fpga

Continue development of Atari 2600 in Verilog. Based on the original work by Daniel Beer.

atari-2600 atari2600 fpga retrogaming verilog

Last synced: 24 Nov 2024

https://github.com/mc256/eecs2021

DO NOT COPY. MAKE SURE U UNDERSTAND.

eecs2021 mips verilog yorkuniversity

Last synced: 24 Nov 2024

https://github.com/susiejojo/sobel_filter

Sobel filter for edge detection in images supporting parallel processing using Verilog on Xilinx ISE 13.4

hdl sobel-filter verilog xilinx-ise

Last synced: 17 Dec 2024

https://github.com/j-m-li/logical16x16

Hardware Description Language for EPROM and FLASH memories

eprom public-domain verilog

Last synced: 18 Nov 2024

https://github.com/polaris000/cs_f342

Lab assignments and some practise done for the Computer Architecture course at BITS Pilani

assembly bits-pilani comparch computer-architecture labs practise verilog

Last synced: 09 Jan 2025

https://github.com/28ritu/alu

An ALU Design in Verilog

alu verilog waveform

Last synced: 22 Dec 2024

https://github.com/madh93/scpu

Simple 16-bit CPU written in Verilog.

cpu datapath verilog

Last synced: 01 Dec 2024

https://github.com/gcerpa01/compe470

Work of my projects I worked on while enrolled in SDSU's COMPE470 Digital Circuits course in Spring 2023

verilog verilog-hdl vivado

Last synced: 17 Jan 2025

https://github.com/arsham-lh/computer-architecture

Code files related to the Computer Architecture course, taught by M. Movahedin

computer-architecture mips-assembly multi-cycle-processor single-cycle-processor verilog

Last synced: 17 Jan 2025

https://github.com/arsham-lh/logic-circuits

Simulation of logic circuits using Verilog, Proteus and other tools.

digital-circuits fsm logic-circuits mealy-machine moore-machine proteus verilog

Last synced: 17 Jan 2025

https://github.com/mthszr/stopwatch-verilog

Projeto da 2ª unidade, para a disciplina de Sistemas Digitais, no qual consiste em desenvolver um Cronômetro Digital, utilizando Verilog com a base de Máquina de Estados Finitos.

verilog verilog-hdl

Last synced: 22 Nov 2024

https://github.com/caite21/cpu-core

8-bit CPU Core Design in Verilog

cpu verilog xilinx-vivado

Last synced: 22 Nov 2024

https://github.com/lsx-s-software/tiny-riscv-cpu

An implementation of RV32I ISA, including a single-cycle version and a pipelined version.

cpu pipeline risc-v verilog

Last synced: 22 Nov 2024

https://github.com/mark-mdo47/fpga_rbg_2_rbgw

Lattice iCE40 FPGA convert WS2812b RGB from ESP32 to SK6812 RGBW

apio esp32-arduino fpga ice40 icestick led sk6812 verilog ws2812b

Last synced: 22 Nov 2024

https://github.com/tanuj-maheshwari/fpga

Configurable FPGA Fabric simulated in Verilog

fpga verilog

Last synced: 22 Nov 2024

https://github.com/cr0a3/hardwarelib

A libary to create asics in short time

asic hardware verilog

Last synced: 22 Nov 2024

https://github.com/clementkim/logic-circuit-verilog

아주대학교 논리회로 - Verilog를 이용한 프로젝트 코드

logic-circuit verilog

Last synced: 15 Dec 2024

https://github.com/tdholmes/digitaldesign-pong

Verilog Pong game designed for Digital Design in December of 2013.

pong verilog

Last synced: 02 Dec 2024

https://github.com/aliiiw/computer-architecture-lab

Implement Mips cpu with Verilog

forwarding mips pipeline verilog

Last synced: 02 Dec 2024

https://github.com/dpieve/university

A resource for students learning programming and personal reference.

assembly cpp haskell haskell-exercises java matlab prolog python shell unifei-university verilog

Last synced: 22 Dec 2024

https://github.com/dyna-bytes/fpga_winter_internship_2020

[Korea University Elementary Particle Physics Lab] Hardware control research using FPGA

fpga rtl verilog vhdl

Last synced: 02 Dec 2024

https://github.com/dyna-bytes/fisr

Specialized FPU for Fast Inverse Square Root Algorithm

fpu verilog

Last synced: 02 Dec 2024

https://github.com/toruniina/brainfxck-circuit

run brainfxck on FPGA

brainfuck verilog

Last synced: 08 Dec 2024

https://github.com/guntas-13/verilog

Compilation of all the Verilog Assignments in the course ES204 - Digital Systems (Spring 2024) - Prof. Joycee Mekie

verilog verilog-hdl

Last synced: 03 Dec 2024

https://github.com/kulp/tappy

tappy is a tiny Verilog driver for PS/2 keyboards, for use in FPGAs

fpga verilog

Last synced: 16 Dec 2024

Verilog Awesome Lists
awesome-hdl 121 awesome-open-hardware-verification 44 ASIC-Design-Roadmap 83 VHDL-Guide 287 CPLD-Guide 287
Verilog Categories
OpenCL Tools, Libraries and Frameworks 138 C/C++ Tools, Libraries and Frameworks 80 C/C++ Learning Resources 68 MATLAB Tools, Libraries, Frameworks 66 Firmware Tools, Libraries, and Frameworks 56 Assembly Learning Resources 36 MATLAB Learning Resources 34 Meta HDL and Transpilers 32 Projects and IPs 31 Firmware Learning Resources 28 Verilog/SystemVerilog Learning Resources 25 Verilog/SystemVerilog Tools 24 Frameworks: 23 OpenCL Learning Resources 22 HLS 16 Tutorials and Courses 💬[Intro](./Tutorials%20and%20Courses/README.md) 15 Tutorials and Courses 15 PSS : Portable test and Stimulus Standard 14 Awesome Awesome ⭐ 12 HDL simulators and compilers 9