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Verilog
Verilog is a widely-used hardware description language (HDL) that enables designers to model, simulate, and synthesize digital circuits. It provides a text-based format for specifying the structure and behavior of electronic systems, making it easier to design complex hardware components such as microprocessors, memory, and communication devices.
- GitHub: https://github.com/topics/verilog
- Wikipedia: https://en.wikipedia.org/wiki/Verilog
- Aliases: hdl, hardware-description-language,
- Last updated: 2025-02-03 00:29:18 UTC
- JSON Representation
https://github.com/anuragnatoo/ele301p
VLSI System Design Practice Lab
activity-factors practice-lab python python-application test-bench verilog vlsi
Last synced: 11 Jan 2025
https://github.com/vincent-g-van/one-time-pad-fpga
64-Bits One-Time Pad on FPGA Board (Nexys 4 DDR Artix-7).
diligent nexys4 one-time-pad otp seven-segment verilog vivado
Last synced: 30 Jan 2025
https://github.com/melchisedech333/verilog-experiments
:space_invader: My studies with Verilog and notions of digital systems.
digital-system-design digital-systems digital-systems-design digital-systems-fundamentals hdl icarus-verilog verilog verilog-code verilog-examples verilog-hdl verilog-project
Last synced: 03 Feb 2025
https://github.com/cmpark0126/mips_32bits
Implements 32bits MIPS with verilog. (18.11.25 ~ 18.12.)
Last synced: 23 Dec 2024
https://github.com/jasonbrave/microsoc
RISC-V SoC
microcontroller risc-v riscv soc system-on-chip systemverilog uart verilog
Last synced: 20 Dec 2024
https://github.com/samiyaalizaidi/pipelined-risc-v-processor
A Pipelined RISC-V Processor with forwarding support and hazard detection.
assembly computer-architecture pipelining processor processor-architecture risc-v verilog vivado
Last synced: 16 Jan 2025
https://github.com/samiyaalizaidi/fpga
Verilog implementation of the basic structure of an FPGA
digital-system-design fpga verilog vivado
Last synced: 16 Jan 2025
https://github.com/pawel2000pl/verilogleddriver
Led RGB driver written in verilog, implemented for Mimas A7 Mini FPGA Development Board
fpga led-controller led-driver pwm pwm-driver systemverilog verilog vivado
Last synced: 22 Jan 2025
https://github.com/ranitmanik/cs-verilog-assignments
A collection of Verilog code snippets and assignments for computer science coursework.
assignment coding iverilog low-level-programming practice practice-programming verilog
Last synced: 28 Jan 2025
https://github.com/vlad-ivanov-name/verilog-zeroall
Resets all register to zero in a Verilog design
Last synced: 31 Jan 2025
https://github.com/coldnew/nand2tetris
My notes and impement on Nand2Tetris courses
coursearea nand2tetris personal-notes verilator verilog
Last synced: 15 Jan 2025
https://github.com/shiro-raven/verilog-mips
A verilog-based MIPS processor with pipelining
assembly mips mips-architecture verilog
Last synced: 01 Feb 2025
https://github.com/qasimwani/karnaugh-map-batch-calculator
Calculates Multiple Karnaugh Maps at once using Selenium and custom built parser. The program then converts the Boolean Expressions into Dataflow Verilog (VHDL)
converts dataflow-verilog karnaugh-map karnaugh-map-solver karnaugh-maps selenium verilog web-scraping
Last synced: 27 Dec 2024
https://github.com/yappy2000d/fpga-make-win
Use the make tool to automate your work in CLI.
Last synced: 25 Jan 2025
https://github.com/theoplayz2/eda-explorer
Инструмент на Python для разведочного анализа данных (EDA) и визуализации, поддерживающий загрузку данных CSV и JSON, с модульной архитектурой ООП. Практическая работа по теме: "Обнаружение и визуализация данных для понимания их сущности" дисциплины "МДК 13.01: Основы применения методов искусственного интеллекта в программировании".
analysis battery-life cqrs csharp data-analysis eeg-analysis exploratorydataanalysis json-visualization matplotlib messaging profile-report python verilog visualization
Last synced: 28 Jan 2025
https://github.com/jjateen/snake-game-verilog
This repository showcases a Verilog-based Snake and Apple Game, developed for the ECL 106: Digital System Design with HDL course. Running on an Altera DE10-Lite FPGA board and displayed on a VGA monitor, players control a snake to collect apples while avoiding obstacles. The snake grows longer with each apple, making the game progressively harder.
altera-fpga de10-lite fpga quartus-prime verilog verilog-project
Last synced: 17 Jan 2025
https://github.com/mthszr/stopwatch-verilog
Projeto da 2ª unidade, para a disciplina de Sistemas Digitais, no qual consiste em desenvolver um Cronômetro Digital, utilizando Verilog com a base de Máquina de Estados Finitos.
Last synced: 22 Jan 2025
https://github.com/wassimhedfi/fpga_adc_pwm_motorcontrol
This repository contains the implementation of a motor speed control system using an FPGA. The speed is adjusted dynamically through a potentiometer, leveraging ADC for analog-to-digital conversion and PWM for precise motor control.
adc de10-lite fpga html motor-speed pwm verilog vhdl
Last synced: 31 Jan 2025
https://github.com/peplxx/morse-coder
This project was made for optional fpga project during F23 Computer Architecture course. This is Quartus Project for turning fpga board into morse coder.
fpga-board fpga-programming morse-code quartus-prime verilog
Last synced: 20 Dec 2024
https://github.com/rogerfan48/course-soph1-hdl
Materials and coursework for Hardware Design Lab (Sophomore Fall). Contains exercises, assignments, and laboratory work.
Last synced: 08 Jan 2025
https://github.com/roscibely/arithmetic-logic-unit
A simple arithmetic logic unit (ALU) with System verilog
Last synced: 21 Jan 2025
https://github.com/elifgokpinar/microprocessor-design
Quartus Project
microprocessor quartus verilog
Last synced: 13 Jan 2025
https://github.com/mohammadmahdi-abdolhosseini/computer-architecture-lab
Computer Architecture Lab - Assignments - Fall 2023
arm-processor fpga modelsim quartus2 systemverilog verilog vhdl
Last synced: 07 Jan 2025
https://github.com/tanuj-maheshwari/fpga
Configurable FPGA Fabric simulated in Verilog
Last synced: 23 Jan 2025
https://github.com/kassane/fpga_course
Testing conducted during verilog studies
Last synced: 13 Jan 2025
https://github.com/kaushalmodi/nim-svvpi
Wrapper for SystemVerilog VPI headers sv_vpi_user.h and vpi_user.h
1364-2005 1800-2017 nim pli systemverilog verilog vpi
Last synced: 16 Jan 2025
https://github.com/kitune-san/kfmmc_v2
Multi media card access controller written in HDL
hdl mmc multimediacard sdc sdcard verilog verilog-hdl
Last synced: 21 Jan 2025
https://github.com/princeranjan03/imageencryption_i-chip
This project focuses on creating a hardware-based encryption and decryption system that implements the Data Encryption Standard (DES) algorithm.
cipher cryptography data-encryption data-encryption-standard encoding encryption-decryption fpga image image-processing opencv rtldesign source-coding verilog verilog-hdl verilog-project vivado xilinx xilinx-vivado
Last synced: 31 Jan 2025
https://github.com/kitune-san/kf76489
KF76489 - 76489-like Digital Complex Sound generator written in SystemVerilog
fpga sn76489 systemverilog verilog
Last synced: 21 Jan 2025
https://github.com/susiejojo/sobel_filter
Sobel filter for edge detection in images supporting parallel processing using Verilog on Xilinx ISE 13.4
hdl sobel-filter verilog xilinx-ise
Last synced: 17 Dec 2024
https://github.com/j-m-li/logical16x16
Hardware Description Language for EPROM and FLASH memories
Last synced: 18 Nov 2024
https://github.com/azazhassankhan/verilogutilitysuite
VerilogUtilitySuite 🚀 Welcome to our SystemVerilog playground! 🤖 Dive into the world of hardware description language (HDL) with our repository, where RTL designs meet creativity.
circuit component-architecture systemverilog verilog
Last synced: 21 Jan 2025
https://github.com/jackson-nestelroad/verilog-mips-processor
Single-cycle 32-bit MIPS processor implemented in SystemVerilog.
Last synced: 29 Jan 2025
https://github.com/polaris000/cs_f342
Lab assignments and some practise done for the Computer Architecture course at BITS Pilani
assembly bits-pilani comparch computer-architecture labs practise verilog
Last synced: 09 Jan 2025
https://github.com/cr0a3/hardwarelib
A libary to create asics in short time
Last synced: 23 Jan 2025
https://github.com/paulchen2713/introduction_to_veriloghdl
Digital System Design Course Practices
Last synced: 23 Jan 2025
https://github.com/davoodeh/verilog2hspice
Do some simple conversions on Verilog files to make them compatible with HSpice
Last synced: 15 Dec 2024
https://github.com/mssola/hdl
Playing around with Hardware Description Languages.
Last synced: 27 Jan 2025
https://github.com/gcerpa01/compe470
Work of my projects I worked on while enrolled in SDSU's COMPE470 Digital Circuits course in Spring 2023
Last synced: 17 Jan 2025
https://github.com/arsham-lh/computer-architecture
Code files related to the Computer Architecture course, taught by M. Movahedin
computer-architecture mips-assembly multi-cycle-processor single-cycle-processor verilog
Last synced: 17 Jan 2025
https://github.com/arsham-lh/logic-circuits
Simulation of logic circuits using Verilog, Proteus and other tools.
digital-circuits fsm logic-circuits mealy-machine moore-machine proteus verilog
Last synced: 17 Jan 2025
https://github.com/tdholmes/digitaldesign-pong
Verilog Pong game designed for Digital Design in December of 2013.
Last synced: 29 Jan 2025
https://github.com/memgonzales/hdl-flip-flop
Compilation of Verilog behavioral models and test benches for the four types of flip-flops (SR, JK, D, and T)
behavioral-modeling computer-architecture flip-flop sequential-circuits verilog
Last synced: 20 Jan 2025
https://github.com/ain1084/audio_level_meter
This is an audio level meter implemented using Verilog HDL.
audio machxo2 verilog visualization
Last synced: 20 Dec 2024
https://github.com/cepdnaclk/e18-co502-rv32im-pipeline-implementation-group4
Single-cycle MIPS-like processor with a memory subsystem including a cache.
computer-architecture risc-v verilog
Last synced: 11 Jan 2025
https://github.com/mark-mdo47/fpga_rbg_2_rbgw
Lattice iCE40 FPGA convert WS2812b RGB from ESP32 to SK6812 RGBW
apio esp32-arduino fpga ice40 icestick led sk6812 verilog ws2812b
Last synced: 22 Jan 2025
https://github.com/youseftareq33/digital_buildcombinationalcircuit_2
Using Verilog HDL on Quartus application build combinational circuit
Last synced: 24 Dec 2024
https://github.com/karagultm/datapath
The project involved extending the processor to support six new instructions: brv, jmxor, nori, blezal, jalpc, and baln. This required modifications to the control logic, the addition of new multiplexers, and the inclusion of status register flags to handle the specific behaviors of these instructions.
mips mips-architecture mips-assembly verilog
Last synced: 24 Dec 2024
https://github.com/assem-elqersh/mips-processor-designs
Comprehensive repository containing Verilog implementations of MIPS processors. Includes both single-cycle and multi-cycle architectures, each in separate directories, with full simulation testbenches and modular design components for educational and development purposes.
computer-architecture educational hardware-designs mips mips-architecture processor-design simulation verilog
Last synced: 27 Jan 2025
https://github.com/clementkim/logic-circuit-verilog
아주대학교 논리회로 - Verilog를 이용한 프로젝트 코드
Last synced: 15 Dec 2024
https://github.com/tdjsnelling/garbled-circuits
Yao’s Garbled Circuits in TypeScript
cryptography garbled-circuits javascript mpc multiparty-computation nodejs oblivious-transfer typescript verilog
Last synced: 15 Dec 2024
https://github.com/aliiiw/computer-architecture-lab
Implement Mips cpu with Verilog
forwarding mips pipeline verilog
Last synced: 30 Jan 2025
https://github.com/chaseruskin/setup-orbit
GitHub Action to install Orbit
action continuous-integration hdl systemverilog utilities verilog vhdl
Last synced: 26 Jan 2025
https://github.com/woolseyworkshop/article-creating-a-configurable-multifunction-logic-gate-in-verilog
Creating A Configurable Multifunction Logic Gate In Verilog Article Resources
Last synced: 29 Dec 2024
https://github.com/woolseyworkshop/article-getting-started-with-the-tinyfpga-bx
Getting Started With The TinyFPGA BX Article Resources
electronics programming tinyfpga-bx verilog
Last synced: 29 Dec 2024
https://github.com/eonu/fpga
Hardware implementations for basic digital circuit designs in Verilog with a Xilinx Artix-7 FPGA chip on a Digilent Basys 3 development board.
artix-7 basys3 circuits digital-design fpga hardware hardware-designs hdl simulation testbench verilog vivado
Last synced: 29 Dec 2024
https://github.com/dpieve/university
A resource for students learning programming and personal reference.
assembly cpp haskell haskell-exercises java matlab prolog python shell unifei-university verilog
Last synced: 22 Dec 2024
https://github.com/mohammadmahdi-abdolhosseini/digital-logic-courses
Digital Systems 1 & 2 + Digital Systems Laboratory 1 + Digital Electronics Circuit +Microprocessor Based and Embedded Design courses projects
Last synced: 07 Jan 2025
https://github.com/abdullahmaqbool22/arithmetic-logic-unit-alu
A final semester project for Digital Logic Data.
Last synced: 29 Dec 2024
https://github.com/bipinoli/vericlash
Implementation of bunch of circuits in Haskell (Clash) and Verilog to learn and compare them
Last synced: 21 Dec 2024
https://github.com/kulp/tappy
tappy is a tiny Verilog driver for PS/2 keyboards, for use in FPGAs
Last synced: 16 Dec 2024
https://github.com/et312/custom_cpu
Custom 16-bit RISC-based CPU with custom control unit, ALU, and memory block designs
Last synced: 16 Dec 2024
https://github.com/carlkidcrypto/digital-systems-engineering
A repo for ECE 440 (Digital Systems Engineering) class projects
systemverilog verilog xilinx-vivado zynq
Last synced: 16 Dec 2024
https://github.com/limpix31/tangmega138kpro-blink
fpga hardware-design hdl system-verilog verilog
Last synced: 07 Jan 2025
https://github.com/rainingcomputers/srp16
SRP16 is free and open ISA for 16-bit CPUs and Microcontrollers.
cpu instruction-set-architecture isa isa-specification microcontrollers open-embedded open-isa risc soft-core verilog
Last synced: 21 Dec 2024
https://github.com/fuwn/iverilog-test-bench
☀️ Icarus Verilog Test-bench Template
Last synced: 10 Dec 2024
https://github.com/namberino/simple-uart
Simple UART implementation in FPGA
Last synced: 20 Jan 2025
https://github.com/andrejchoo/cpldctrum
ZX Spectrum clone on CPLD
cpld divmmc verilog zx-spectrum
Last synced: 11 Dec 2024
https://github.com/andrejchoo/avr_like_core_on_verilog
Soft core with support for the AVR8 instructions on verilog
Last synced: 11 Dec 2024
https://github.com/seojuncha/fromthetransistor-fork
geohot's fromthetransistor project. Create a repo on my own because of the contribution map!!
assembler assembly c compiler fromthetransistor python uart verilog
Last synced: 11 Dec 2024
https://github.com/aledpl5/rock-paper-scissors-circuit
Uni project about the game rock-paper-scissors
blif circuit datapath datapath-design finate-state-machine sis systemverilog verilog
Last synced: 05 Jan 2025
https://github.com/idorobots/upduino-blinky
Two simple Upduino projects that blink an RGB LED in various ways.
blinky fpga ice40 ice40up5k led upduino upduino-board verilog
Last synced: 20 Dec 2024
https://github.com/skpro-glitch/resume
Find my resume, encapsulating my most prominent projects and experiences relevant for an entry level Hardware Engineering role. - Soham Kapur
algorithms-and-data-structures cadence cadence-virtuoso drone electronics-engineering java java-programming ltspice matlab soham-kapur sohamkapur team-aviators-international uav verilog verilog-hdl verilog-processor vit-chennai vit-university vitc vitchennai
Last synced: 12 Dec 2024
https://github.com/markmll/todaystart-a153
As-shipped demo for the Altera Cyclone TodayStart-A153 board. Requires Quartus-II 10.1 SP1 minimum.
Last synced: 21 Dec 2024
https://github.com/abstractmachines/verilog-shift-register
A shift register in Verilog. Bidirectional pin use.
embedded-systems hardware shift-register verilog
Last synced: 12 Dec 2024
https://github.com/jminjares4/digital-system-2-template
Digital System 2 Template
Last synced: 10 Jan 2025
https://github.com/mtaciano/fpgmips
Um processador baseado na arquitetura MIPS 32bits no FPGA DE2-115.
Last synced: 12 Dec 2024
https://github.com/rehankarthikchandralal/implementation-of-a-configurable-neural-processing-unit-with-input-and-weight-stationary-dataflows
Used Verilog to design an entire NPU that supports two different kinds of dataflows to enable data reuse in order to reduce power consumption and resource utilization
neural-network-hardware verilog
Last synced: 17 Dec 2024
https://github.com/risto97/socmake
Build system for RTL and SoC designs
cmake cpu hardware rtl simulation systemc systemonchip systemrdl verilog
Last synced: 21 Dec 2024
https://github.com/shuregg/riscv-simple-cpu
Creating a risc-v processor
cpu risc-v riscv riscv32 rtl systemverilog verification verilog verilog-hdl
Last synced: 13 Dec 2024
https://github.com/shuregg/fpga-practicum
learning about FPGA
fpga fpga-programming rtl systemverilog verilog vivado xilinx
Last synced: 13 Dec 2024
https://github.com/shuregg/miet-interfaces
Interfaces of computing systems
interfaces protocols verilog verilog-hdl
Last synced: 13 Dec 2024
https://github.com/rpigor/tpsim
TPSim (Timing and Power Simulator) is a gate-level circuit simulator with timing and power estimation capabilities
eda power-analysis simulator timing-analysis verilog
Last synced: 06 Jan 2025
https://github.com/akielaries/hwverif
Sandbox for exploring Hardware Verification
Last synced: 20 Jan 2025
https://github.com/lasithaamarasinghe/uart-implementation-in-fpga
This is a group assignment done under semester 4 module EN2111:Electronic Circuit Design, .
fpga quartus-prime uart verilog
Last synced: 10 Jan 2025
https://github.com/mohamad-shosha/alu-verilog-proteus
This 4-bit ALU design project has been implemented as part of the [Computer Aided Design] in the university , where we applied Verilog for hardware design and Proteus for simulation.
Last synced: 28 Dec 2024
https://github.com/urish/tt06-spell
A minimal, stack-based programming language created for The Skull CTF
Last synced: 11 Jan 2025
https://github.com/dev-ritik/calculator
Xilinx college project
calculator college-project gui java-applet verilog xilinx
Last synced: 30 Jan 2025
