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Verilog
Verilog is a widely-used hardware description language (HDL) that enables designers to model, simulate, and synthesize digital circuits. It provides a text-based format for specifying the structure and behavior of electronic systems, making it easier to design complex hardware components such as microprocessors, memory, and communication devices.
- GitHub: https://github.com/topics/verilog
- Wikipedia: https://en.wikipedia.org/wiki/Verilog
- Aliases: hdl, hardware-description-language,
- Last updated: 2025-02-08 00:27:45 UTC
- JSON Representation
https://github.com/xyene/t258-cpu
A simple RISC CPU implemented in Verilog, as well as compilation toolchain for it.
assembler compiler cpu verilog
Last synced: 18 Jan 2025
https://github.com/jn513/grande-risco-5
Processador RISC-V multi ciclo com implementação RV32IMB construído em alguns dias de folga.
arquitetura fpga risc-v riscv riscv32 verilog verilog-hdl
Last synced: 08 Feb 2025
https://github.com/sefakcmn00/fpga-vhdl-samples-
Simple logic gate applications were implemented using FPGA VHDL language. These are; counter counter circuit, float point, multix.
floating-point fpga verilog vhdl
Last synced: 14 Nov 2024
https://github.com/ahmedhamed3699/aes-encryption
An AES encryption and decryption project that follows SPI (Serial Peripheral Interface) specification. Implemented in Verilog
aes aes-encryption fpga logic-design spi verilog
Last synced: 08 Jan 2025
https://github.com/bartpleiter/fpgc5
A completely self designed (game) computer, implemented in hardware using an FPGA. Basically every component is self designed, from the ISA up to the PCB and software. Project exists to learn more about the fundamentals of computers and to improve my Verilog skills
assembler c compiler computer-architecture cpu fpga gpu hardware software verilog
Last synced: 07 Nov 2024
https://github.com/dineshpinto/timetagger
FPGA programming for nanosecond photon counting
c fpga fpga-programming linux photonics picosecond swig-binding verilog
Last synced: 04 Feb 2025
https://github.com/xtrinch/icestick-fpga-uart
UART + UART packets encoding/decoding + pc reader program for Lattice icestick
fpga icestorm-toolchain verilog
Last synced: 21 Dec 2024
https://github.com/ain1084/serial_audio_decoder
Serial audio data (I2S or Left justified) decoder
Last synced: 20 Dec 2024
https://github.com/wvangansbeke/smart-card-rsa
RSA alogrithm with hardware/software co-design
Last synced: 27 Dec 2024
https://github.com/sondosaabed/verilog-digital-circuits
Bunch of circuits designed in a Digital Circuits BZU
Last synced: 25 Dec 2024
https://github.com/samiyaalizaidi/equalizer
Fixed Point FPGA-based Hardware Implementation of a 32-tap Low Pass FIR Filter for Audio Applications
audio-equalizer audio-processing digital-signal-processing digital-signal-processing-filters digital-system-design digital-systems-design equalizer filter-design fir-filters fpga verilog verilog-hdl xilinx-vivado
Last synced: 16 Jan 2025
https://github.com/aditeyabaral/up-down-counter
A simple up-down counter made using icarus verilog as a part of the Digital Design and Computer Organization course (UE18CS201) at PES University.
counter digital-design icarus-verilog logic-programming verilog verilog-project
Last synced: 17 Jan 2025
https://github.com/ekarton/pacman-on-fpga
CSC 258 Final Project: Pacman on an FPGA with Verilog
Last synced: 24 Jan 2025
https://github.com/markmll/tang_nano_as_shipped
A close approximation of the demo code on Sipeed Tang Nano boards as shipped.
Last synced: 21 Dec 2024
https://github.com/pvgupta24/von-neumann-architecture-cpu
Implementation of 8-Bit CPU based on Von-Neumann Architechture in HDL
cpu cpu-simulator verilog verilog-hdl von-neumann
Last synced: 06 Jan 2025
https://github.com/susiejojo/mips_processor
A simple MIPS processor implemented using Verilog capable of supporting basic I,J and R type instructions. Built using Xilinx Vivado 2019.1
mips mips-architecture processor verilog
Last synced: 17 Dec 2024
https://github.com/cw1997/graphical_card
a graphical card for displaying text on VGA text mode by D-Sub port
graphical-programming hardware hardware-designs systemverilog-simulation verilog verilog-project
Last synced: 27 Jan 2025
https://github.com/jeffdecola/control-fpga-via-raspi-and-webserver
Control a FPGA via a Raspberry Pi and a Webserver.
arty-s7 fpga go golang gpio pmod raspberry-pi raspi verilog webserver xilinx-fpga xilinx-vivado
Last synced: 25 Oct 2024
https://github.com/UW-PHARM/BitSAD
A domain-specific language for bitstream computing
bitstream code-generation compiler-plugin scala stochastic-computing verilog
Last synced: 15 Oct 2024
https://github.com/shyamal-anadkat/wisc-sp13
CS 552 term project : functional design of a microprocessor called the WISC-SP13
cs552 hardware-designs mips-assembly processor processor-architecture verilog verilog-hdl
Last synced: 16 Dec 2024
https://github.com/rohittp0/chipon
PyTorch to Verilog transpiler
hardware-designs pytorch verilog
Last synced: 31 Oct 2024
https://github.com/cw1997/verilog-parser
Verilog HDL Parser
parser parsers verilog verilog-hdl verilog-simulator
Last synced: 27 Jan 2025
https://github.com/sped0n/ada
An Artix 7 based dual channel oscilloscope.
artix-7 ft232h oscilloscope verilog xc7a35t
Last synced: 24 Dec 2024
https://github.com/yasnakateb/aes
🔐 Hardware Implementation Of AES Algorithm in Verilog HDL
aes aes-128 aes-encryption encryption encryption-algorithm icarus-verilog iverilog verilog verilog-hdl
Last synced: 20 Jan 2025
https://github.com/dvvcz/viva
Experimental cli to create HDL projects using Vivado, outside of their IDE.
cli hardware hdl package-manager rust systemverilog verilog vivado
Last synced: 05 Jan 2025
https://github.com/abhishek010397/programming-risc-v
Design of RISC V CPU Core
advanced-computer-architecture microprocessor multithreading python3 risc-v verilog
Last synced: 23 Dec 2024
https://github.com/gergoerdi/clash-bounce-bench
Benchmark for various methods of simulating Clash
benchmark c clash haskell sdl2 simulation verilator verilog
Last synced: 17 Jan 2025
https://github.com/pconst/xilinx_max_power
Stress test power subsystem of your Xilinx FPGA board
arty board cooling development digilent fpga power shift-register soc systemverilog test ultrascale verilog xilinx zinq
Last synced: 11 Jan 2025
https://github.com/raleighlittles/basys3countdownclock
Extremely basic countdown clock project for the Basys 3 FPGA development board.
basys-3 basys3 fpga hdl seven-segment-display verilog vivado xdc xilinx
Last synced: 26 Jan 2025
https://github.com/meiniki/logip
Logic Analyzer IP Core
amd asic basys3 digital formal-verification fpga hardware-description-language hdl ip logicanalyzer logip measurements ols sump symbiyosys systemverilog verilog vivado xilinx
Last synced: 23 Jan 2025
https://github.com/donn/swiftlog
An IcarusVerilog VPI bridge for the Swift Programming Language.
Last synced: 27 Jan 2025
https://github.com/amirhnajafiz-university/s3lc02
Logical circuits course final project.
circuit internet-of-things logical-circuits verilog
Last synced: 26 Dec 2024
https://github.com/zannatul-naim/digital-system-design
Digital System Design Lab Codes using Verilog
adder d-flipflop flipflop full-adder half-adder jk-flipflop ripple-carry-adder t-flipflop verilog
Last synced: 26 Dec 2024
https://github.com/gogolb/ee175
EE 175 Senior Design. Multibaseline Stereo Camera
computer-vision matlab ov7670 senior-design slam stereo-vision university-course university-project verilog vivado xilinx zynq
Last synced: 01 Dec 2024
https://github.com/can-lehmann/hdl.cpp
Register-transfer Level Intermediate Representation
cpp fpga intermediate-representation rtl verilog
Last synced: 24 Oct 2024
https://github.com/chaseruskin/verb
An approachable testing framework for digital hardware
framework python simulation system-verilog testing verification verilog vhdl
Last synced: 14 Jan 2025
https://github.com/algosup/2024-2025-project-1-fpga-team-7
This version of the "Frogger" game is made using a "go-board" and the "verilog" programming language. It takes only the road part of the original game and is made to be used with a vga screen.
frogger frogger-game go-board-game verilog
Last synced: 16 Jan 2025
https://github.com/dineshpinto/stm32f4
Combining an FPGA, µC and AWG for nanosecond photon counting
assembly awg c microcontroller photonics verilog
Last synced: 04 Feb 2025
https://github.com/muhammadtalhasami/rv32i_single_cycle
This repository contains an implementation of a RV32I fetch pipeline microprocessor. The RV32I is a 32-bit RISC-V instruction set architecture, with the 'I' extension indicating the base integer instructions.
fetch-stage-pipeline gtkwave hardware-designs muhammadtalhasami-github- pipeline-processor risc-v-assembly risc-v-pipeline risc-v-processor risc-v-processor-images rv32i rv32i-processor single-cycle-processor single-cycle-processor-gtkwave-image system-verilog system-verilog-codes verilator verilog verilog-code-examples verilog-codes vhdl
Last synced: 25 Dec 2024
https://github.com/alokmenghrajani/adventofcode2018
Advent of Code 2018. Solutions using Verilog + icestick fpga! ☃️🎄🎁🦌🎅
2018 advent-of-code-2018 advent-of-code-2018-fpga adventofcode adventofcode2018 fpga solutions upping-the-ante verilog
Last synced: 25 Jan 2025
https://github.com/akhilrai28/single-port-ram
This project implements a single-port RAM using Verilog. The design simulates a memory module with a single read/write port, supporting basic memory operations like data storage and retrieval. It includes testbenches for functional verification and timing analysis to ensure reliable operation.
digital-circuits fpga fpga-programming hardware hardware-description-language memory-design ram single-port synchronous testbench verilog
Last synced: 08 Feb 2025
https://github.com/hashirshoaeb/verilog-codes
This repository is to help macOS and linux users who have just started learning verilog.
assignment getting-started lab-tasks learning-verilog linux-users macos scansion verilog vscode vscode-plugin
Last synced: 06 Jan 2025
https://github.com/kaushalmodi/nim-systemverilog-vpi
Using Nim to interface with Verilog and SystemVerilog test benches via VPI
1364-2005 1800-2017 c cpp nim pli systemverilog verilog vpi
Last synced: 15 Nov 2024
https://github.com/asankasovis/eight_bit_computer
🎛️ FPGAs are an interesting invention that is expected to revolutionize the digital industry. This series will focus on building the 8-bit computer that Ben Eater built on his youtube channel. However, it will be done not with actual chips and hardware, but with Verilog code and FPGA simulations.
8bit beneater computer fpga fpga-programming verilog
Last synced: 02 Feb 2025
https://github.com/akhilrai28/gravity-accelerator
This project implements a gravity accelerator using Verilog and Vivado. It simulates the physics of gravitational acceleration, calculating velocity and position over time within a digital circuit environment. The project includes testbenches and waveform analysis to ensure accurate simulation and performance.
digital-simulation fpga gravity-algorithm gravity-model gravity-simulation hardware hardware-acceleration hardware-designs physics-simulation testbench verilog vivado
Last synced: 08 Feb 2025
https://github.com/eyantra698sumanto/digital-design-on-fpga
This repo contains documentation of the "VSD Open Digital-Design-on-FPGA" tutorial.
fpga makerchip systemverilog tl-verilog verilog virtual-fpga vsd
Last synced: 09 Jan 2025
https://github.com/yugr/parmatch
A simple script for finding unbound parameters in Verilog module instantiations.
static-analysis static-analyzer verilog
Last synced: 27 Dec 2024
https://github.com/calint/tang-nano-20k--riscv
riscv rv32i tang-nano-20k verilog
Last synced: 10 Jan 2025
https://github.com/shyamal-anadkat/the-11-of-us
adc ece551 flight-controller hdl integrator quadcopter synthesis system-verilog uart verilog vhdl
Last synced: 16 Dec 2024
https://github.com/wyvernsemi/lm32fpga
FPGA development board (DE1) targetted lm32 based systems design for Verilog
altera cpu cyclone fpga latticemico32 modelsim python3 quartus verilog
Last synced: 06 Feb 2025
https://github.com/daulpavid/verilog_template
Boilerplate project template for verilog that includes directories for simulation, documentation, and formal verification.
cmake verilator verilog verilog-template
Last synced: 15 Jan 2025
https://github.com/ain1084/audio_echo_effect
Simple echo effect implementation with digital audio processing.
audio-processing i2s-audio lattice-fpga verilog
Last synced: 20 Dec 2024
https://github.com/z4yx/thinpad-controller-zynq
RTL project for the controller SoC on Thinpad
Last synced: 29 Jan 2025
https://github.com/liu42/processor
《计算机组成原理》课程设计，基于 MIPS 的流水线 CPU 系统设计。
architecture computer-architecture course-project cpu fpga homework-project mips mips-architecture mips-processor pipeline verilog
Last synced: 21 Dec 2024
https://github.com/cpehle/cascade
Cycle based C++ hardware simulation infrastructure
Last synced: 08 Feb 2025
https://github.com/yasnakateb/uartcommunication
☎️ UART Communication Implementation in Verilog HDL
icarus-verilog iverilog serial-communication uart uart-interface uart-protocol uart-verilog verilog
Last synced: 20 Jan 2025
https://github.com/pvgupta24/cse-labs
Dump for CSE Lab assignments and programs
algorithms c computer-architecture cpp data-structures mips opengl verilog
Last synced: 06 Jan 2025
https://github.com/chenqianhe/learnprofessionalbasiccoursesincomputerscience
Learn Professional Basic Courses in Computer Science计算机专业基础课程学习
assembly computer-network computer-science computer-system-structure cpp operating-system principle-of-computer-composition professional-basic-courses verilog
Last synced: 19 Jan 2025
https://github.com/samridhisainii/digitaldesign
These are the question of digital design lab from our subject digital design lab which were done in lab
Last synced: 28 Jan 2025
https://github.com/urish/tt05-silife-8x8
Game of Life in Silicon (8x8)
game-of-life tiny-tapeout verilog
Last synced: 11 Jan 2025
https://github.com/viktor-prutyanov/fpga-ir
IR receiver with UART interface
fpga ir-receiver remote-control verilog
Last synced: 05 Feb 2025
https://github.com/kareimgazer/pci_target_device
Verilog simulation for a Target Device on a PCI bus with read and write transactions.
pci pci-devices verilog xilin xilinx-vivado
Last synced: 03 Feb 2025
https://github.com/tomarus/midirouter
CMOD-A7 FPGA MIDI Merger/Router/Switch.
Last synced: 08 Feb 2025
https://github.com/awrsha/logical-circuit-laboratory
verilog exercises for LC Lab at Qazvin islamic azad university
Last synced: 12 Jan 2025
https://github.com/manighazaee/cpu
CPU architecture implemented in Verilog and its assembler in Rust.
architecture assembler cpu rust verilog
Last synced: 30 Jan 2025
https://github.com/akhilrai28/alarm-clock
This project implements a fully functional digital alarm clock using Verilog and Vivado. The design includes features such as setting the time, alarm functionality, and real-time clock display. The project simulates clock timing and alarm triggers, with testbenches for verifying accuracy and reliability on FPGA.
alarm alarm-clock clock fpga hardware real-time simulation testbench verilog vivado
Last synced: 08 Feb 2025
https://github.com/yaxsomo/iris_cubesat
This Repository is dedicated to FPGA development of the IRIS CubeSat
aerospace cubesat fpga free-space-optical-communiucation satellite verilog vhdl vivado xilinx
Last synced: 11 Jan 2025
https://github.com/muhammadtalhasami/sv_verilator
System verilog learning journey. Here in this repo you learn about how to write system verilog test bench using verilator tool a c++ test bench. Verilator is basically a 2 state tool .
system-verilog-testbench systemverilog testbench verification verilator- verilator-testbench verilog verilog-hdl
Last synced: 06 Nov 2024
https://github.com/jgroman/fpga-tangprimer25k-experiments
Learning digital design with Tang Primer 25K
Last synced: 20 Jan 2025
https://github.com/yugr/gatecheck
Yet another Verilog static analyzer
clock-g gating static-analysis static-analyzer verilog
Last synced: 27 Dec 2024
https://github.com/aben20807/computer_organization
1052_計算機組織 COMPUTER ORGANIZATION
cache cpu datapath pipeline single-cycle verilog
Last synced: 16 Jan 2025
https://github.com/sahilmgandhi/m152b-fall2018
CS M152B Codebase Fall 2018
c color-recognition gyroscope hdmi microblaze verilog xilinx-fpga
Last synced: 10 Jan 2025
https://github.com/lebrancconvas/verilog-playground
Verilog Playground.
digital-electronics logic-gates verilog
Last synced: 08 Jan 2025
https://github.com/grachale/microarchitecture_risc-v_isa
Design of a Processor Microarchitecture Supporting a Chosen Subset of RISC-V ISA Instructions.
assembly isa microarchitecture risc-v verilog
Last synced: 13 Jan 2025
https://github.com/kigawas/mipscpu
A single cycle CPU running on Xilinx Spartan 6 XC6LX16-CS324, supporting 31 MIPS instructions.
educational-project mips verilog
Last synced: 10 Jan 2025
https://github.com/harikrishnan669/verilog
KTU S4 DIGITAL LAB PROGRAMS (VERILOG)
Last synced: 27 Jan 2025
https://github.com/byte-me404/jku-tt06-ps2-morse-encoder
Custom ASIC design which decodes a PS/2 keyboard, furthermore it encodes and outputs the data as morse code
asic ps2-keyboard tinytapeout verilog
Last synced: 05 Jan 2025
https://github.com/eomielan/16-bit-risc-machine
16-bit CPU architecture implementation and verification using SystemVerilog
cpu-architecture systemverilog verilog
Last synced: 30 Dec 2024
https://github.com/yvesemmanuel/introduction_verilog
digital systems
digital-systems verilog verilog-components verilog-project
Last synced: 16 Jan 2025
https://github.com/yvesemmanuel/microwave
second project - Digital System
digital-systems verilog verilog-components verilog-project
Last synced: 16 Jan 2025
https://github.com/ehsanshahbazii/digital-vlsi-system-design-projects
سورس کد پروژه های درس طراحی سیستم های دیجیتال برنامه پذیر دانشگاه تبریز مقطع کارشناسی رشته مهندسی کامپیوتر
verilog verilog-code verilog-components verilog-project vlsi
Last synced: 10 Nov 2024
