https://github.com/sondosaabed/verilog-digital-circuits

Bunch of circuits designed in a Digital Circuits BZU

circuit digital verilog

Last synced: 25 Dec 2024

https://github.com/ahmedhamed3699/aes-encryption

An AES encryption and decryption project that follows SPI (Serial Peripheral Interface) specification. Implemented in Verilog

aes aes-encryption fpga logic-design spi verilog

Last synced: 08 Jan 2025

https://github.com/markmll/tang_nano_as_shipped

A close approximation of the demo code on Sipeed Tang Nano boards as shipped.

fpga verilog vhdl

Last synced: 21 Dec 2024

https://github.com/jeffdecola/control-fpga-via-raspi-and-webserver

Control a FPGA via a Raspberry Pi and a Webserver.

arty-s7 fpga go golang gpio pmod raspberry-pi raspi verilog webserver xilinx-fpga xilinx-vivado

Last synced: 25 Oct 2024

https://github.com/rejunity/zero-to-asic-wrapped-parallax

Tiny experimental ASIC design for efabless/OpenLane fab.

asic efabless fpga openlane verilog

Last synced: 24 Nov 2024

https://github.com/xtrinch/icestick-fpga-uart

UART + UART packets encoding/decoding + pc reader program for Lattice icestick

fpga icestorm-toolchain verilog

Last synced: 21 Dec 2024

https://github.com/cw1997/verilog-parser

Verilog HDL Parser

parser parsers verilog verilog-hdl verilog-simulator

Last synced: 28 Nov 2024

https://github.com/samiyaalizaidi/equalizer

Fixed Point FPGA-based Hardware Implementation of a 32-tap Low Pass FIR Filter for Audio Applications

audio-equalizer audio-processing digital-signal-processing digital-signal-processing-filters digital-system-design digital-systems-design equalizer filter-design fir-filters fpga verilog verilog-hdl xilinx-vivado

Last synced: 16 Jan 2025

https://github.com/jn513/pequeno-risco-5

Processador RISC-V de ciclo único com implementação RV32I construído em alguns dias de folga.

arquitetura risc-v riscv riscv32 verilog verilog-hdl

Last synced: 15 Dec 2024

https://github.com/rejunity/tt06-psg-saa1099

TinyTapeout submission with the SAA1099 a 6-voice programmable sound generator (PSG) chip from Philips.

chip psg retro saa1099 sfx sound tapeout verilog

Last synced: 24 Nov 2024

https://github.com/mattjesc/efficient-fpga-cnn-accelerator

Efficient FPGA-Based Accelerator for Convolutional Neural Networks

ai asic cnn fpga ml systemverilog verilog vhdl vivado vlsi

Last synced: 18 Jan 2025

https://github.com/calint/tang-nano-20k--riscv

riscv rv32i tang-nano-20k verilog

Last synced: 10 Jan 2025

https://github.com/yasnakateb/aes

🔐 Hardware Implementation Of AES Algorithm in Verilog HDL

aes aes-128 aes-encryption encryption encryption-algorithm icarus-verilog iverilog verilog verilog-hdl

Last synced: 20 Jan 2025

https://github.com/cw1997/graphical_card

a graphical card for displaying text on VGA text mode by D-Sub port

graphical-programming hardware hardware-designs systemverilog-simulation verilog verilog-project

Last synced: 28 Nov 2024

https://github.com/chaseruskin/verb

An approachable testing framework for digital hardware

framework python simulation system-verilog testing verification verilog vhdl

Last synced: 14 Jan 2025

https://github.com/sped0n/ada

An Artix 7 based dual channel oscilloscope.

artix-7 ft232h oscilloscope verilog xc7a35t

Last synced: 24 Dec 2024

https://github.com/raleighlittles/basys3countdownclock

Extremely basic countdown clock project for the Basys 3 FPGA development board.

basys-3 basys3 fpga hdl seven-segment-display verilog vivado xdc xilinx

Last synced: 28 Nov 2024

https://github.com/can-lehmann/hdl.cpp

Register-transfer Level Intermediate Representation

cpp fpga intermediate-representation rtl verilog

Last synced: 24 Oct 2024

https://github.com/eyantra698sumanto/digital-design-on-fpga

This repo contains documentation of the "VSD Open Digital-Design-on-FPGA" tutorial.

fpga makerchip systemverilog tl-verilog verilog virtual-fpga vsd

Last synced: 09 Jan 2025

https://github.com/teddy-van-jerry/sdr-psk-fpga

Dual-Mode PSK Transceiver on SDR With FPGA

amd bpsk costas-loop demodulation fpga gardner modulation psk qpsk sdr software-defined-radio synchronization transceiver verilog vivado xilinx zynq zynq-7000 zynq-7020

Last synced: 03 Dec 2024

https://github.com/jn513/grande-risco-5

Processador RISC-V multi ciclo com implementação RV32I construído em alguns dias de folga.

arquitetura fpga risc-v riscv riscv32 verilog verilog-hdl

Last synced: 15 Dec 2024

https://github.com/akhilrai28/gravity-accelerator

This project implements a gravity accelerator using Verilog and Vivado. It simulates the physics of gravitational acceleration, calculating velocity and position over time within a digital circuit environment. The project includes testbenches and waveform analysis to ensure accurate simulation and performance.

digital-simulation fpga gravity-algorithm gravity-model gravity-simulation hardware hardware-acceleration hardware-designs physics-simulation testbench verilog vivado

Last synced: 15 Dec 2024

https://github.com/akhilrai28/single-port-ram

This project implements a single-port RAM using Verilog. The design simulates a memory module with a single read/write port, supporting basic memory operations like data storage and retrieval. It includes testbenches for functional verification and timing analysis to ensure reliable operation.

digital-circuits fpga fpga-programming hardware hardware-description-language memory-design ram single-port synchronous testbench verilog

Last synced: 15 Dec 2024

https://github.com/gogolb/ee175

EE 175 Senior Design. Multibaseline Stereo Camera

computer-vision matlab ov7670 senior-design slam stereo-vision university-course university-project verilog vivado xilinx zynq

Last synced: 01 Dec 2024

https://github.com/gergoerdi/clash-bounce-bench

Benchmark for various methods of simulating Clash

benchmark c clash haskell sdl2 simulation verilator verilog

Last synced: 17 Jan 2025

https://github.com/pconst/xilinx_max_power

Stress test power subsystem of your Xilinx FPGA board

arty board cooling development digilent fpga power shift-register soc systemverilog test ultrascale verilog xilinx zinq

Last synced: 11 Jan 2025

https://github.com/hashirshoaeb/verilog-codes

This repository is to help macOS and linux users who have just started learning verilog.

assignment getting-started lab-tasks learning-verilog linux-users macos scansion verilog vscode vscode-plugin

Last synced: 06 Jan 2025

https://github.com/yugr/parmatch

A simple script for finding unbound parameters in Verilog module instantiations.

static-analysis static-analyzer verilog

Last synced: 27 Dec 2024

https://github.com/mattvenn/rgb_mixer

Project 2.1 RGB Colour Mixer

hdl simulation verilog

Last synced: 15 Dec 2024

https://github.com/kenny2github/v2mc

Synthesize Verilog to Minecraft redstone

hdl minecraft redstone verilog yosys

Last synced: 20 Dec 2024

https://github.com/dvvcz/viva

Experimental cli to create HDL projects using Vivado, outside of their IDE.

cli hardware hdl package-manager rust systemverilog verilog vivado

Last synced: 05 Jan 2025

https://github.com/donn/swiftlog

An IcarusVerilog VPI bridge for the Swift Programming Language.

pli swift verilog vpi

Last synced: 28 Nov 2024

https://github.com/cheyao/achieve-core

RISC-V SoC + OS

core risc-v soc verilog

Last synced: 04 Jan 2025

https://github.com/kaushalmodi/nim-systemverilog-vpi

Using Nim to interface with Verilog and SystemVerilog test benches via VPI

1364-2005 1800-2017 c cpp nim pli systemverilog verilog vpi

Last synced: 15 Nov 2024

https://github.com/rejunity/tt05-psg-ay8913

TinyTapeout submission with the AY-3-8913 a 3-voice programmable sound generator (PSG) chip from General Instruments.

asic ay-3-8910 ay-3-8913 ay8910 chip psg retro sfx sound tapeout verilog ym2149 ymz294

Last synced: 13 Oct 2024

https://github.com/zannatul-naim/digital-system-design

Digital System Design Lab Codes using Verilog

adder d-flipflop flipflop full-adder half-adder jk-flipflop ripple-carry-adder t-flipflop verilog

Last synced: 26 Dec 2024

https://github.com/rj45/rjsc5

rjsc5 a 16-bit RISC-V CPU

cocotb cpu risc-v verilog

Last synced: 02 Jan 2025

https://github.com/muhammadtalhasami/rv32i_single_cycle

This repository contains an implementation of a RV32I fetch pipeline microprocessor. The RV32I is a 32-bit RISC-V instruction set architecture, with the 'I' extension indicating the base integer instructions.

fetch-stage-pipeline gtkwave hardware-designs muhammadtalhasami-github- pipeline-processor risc-v-assembly risc-v-pipeline risc-v-processor risc-v-processor-images rv32i rv32i-processor single-cycle-processor single-cycle-processor-gtkwave-image system-verilog system-verilog-codes verilator verilog verilog-code-examples verilog-codes vhdl

Last synced: 25 Dec 2024

https://github.com/buhe/study_fpga

💾 fpga study with open source tools (on macos)

chisel chisel3 fpga hardware tang-nano verilog

Last synced: 01 Jan 2025

https://github.com/algosup/2024-2025-project-1-fpga-team-7

This version of the "Frogger" game is made using a "go-board" and the "verilog" programming language. It takes only the road part of the original game and is made to be used with a vga screen.

frogger frogger-game go-board-game verilog

Last synced: 16 Jan 2025

https://github.com/amirhnajafiz-university/s3lc02

Logical circuits course final project.

circuit internet-of-things logical-circuits verilog

Last synced: 26 Dec 2024

https://github.com/abhishek010397/programming-risc-v

Design of RISC V CPU Core

advanced-computer-architecture microprocessor multithreading python3 risc-v verilog

Last synced: 23 Dec 2024

https://github.com/pirate-emperor/cipherx

CipherX is a verification project for Advanced Encryption Standard (AES-128) using Universal Verification Methodology (UVM). It leverages Verilog, SystemVerilog, and Python to ensure robust encryption algorithm validation, integrating comprehensive UVM components and tests.

aes-128 cryptography cryptography-algorithms dataencryption dataencryptionstandards digitaldesign encrytption hardwareverification python security testing-framework uvm verification verilog

Last synced: 04 Dec 2024

https://github.com/meetps/ee-214

VHDL and Verilog Codes for Digital Lab.

digital-logic fpga verilog vhdl

Last synced: 04 Jan 2025

https://github.com/viktor-prutyanov/fpga-ir

IR receiver with UART interface

fpga ir-receiver remote-control verilog

Last synced: 12 Dec 2024

https://github.com/daulpavid/verilog_template

Boilerplate project template for verilog that includes directories for simulation, documentation, and formal verification.

cmake verilator verilog verilog-template

Last synced: 15 Jan 2025

https://github.com/bugenzhao/mips

👨🏻‍💻 Pipelined MIPS I CPU with 49 instructions & multiplication & direct-mapped cache in Verilog.

mips simulator verilog

Last synced: 23 Nov 2024

https://github.com/gyeonghokim/riscv_core

building 32bit risc-v core and Machine Learning for Branch Prediction

fpga risc-v verilog

Last synced: 29 Dec 2024

https://github.com/eomielan/16-bit-risc-machine

16-bit CPU architecture implementation and verification using SystemVerilog

cpu-architecture systemverilog verilog

Last synced: 30 Dec 2024

https://github.com/bryanlimy/flappybird-verilog

Flappy-Bird-liked game in Verilog

flappy-bird flappy-bird-game verilog

Last synced: 17 Dec 2024

https://github.com/djg/cpu

CPU - Verilog + Rust

cmake fpga rtl rust verilator verilog

Last synced: 19 Dec 2024

https://github.com/alyssonmach/logic-circuits

Simulations made in the UFCG logic circuit laboratory.

laboratory logic-circuit logisim quartus ufcg verilog

Last synced: 24 Dec 2024

https://github.com/suda-morris/suda_riscv

Playing with FPGA and RISC-V

chisel3 fpga risc-v verilog

Last synced: 30 Dec 2024

https://github.com/sedhossein/verilog-bcd-counter-jk-flip-flop

this source is Commercial bcd counter that built with Jk flip-flop in verilog

bcd counter flip-flop logic verilog

Last synced: 17 Jan 2025

https://github.com/amirreza81/digital-systems-design

Digital Systems Design - Spring 2023 - Sharif University of Technology

assembly digital-system-design verilog

Last synced: 05 Jan 2025

https://github.com/kigawas/mipscpu

A single cycle CPU running on Xilinx Spartan 6 XC6LX16-CS324, supporting 31 MIPS instructions.

educational-project mips verilog

Last synced: 10 Jan 2025

https://github.com/urish/tt05-silife-8x8

Game of Life in Silicon (8x8)

game-of-life tiny-tapeout verilog

Last synced: 11 Jan 2025

https://github.com/hywooo/docker-bsv-wsl2

🐋Docker for Bluespec SystemVerilog (BSV) on WSL2, compatible with WangXuan95/BSV_Tutorial_cn. 适用于BSV中文教程的Docker BSV （WSL2）环境。

bluespec-systemverilog bsv docker dockerfile packages systemverilog verilog vivado

Last synced: 29 Oct 2024

https://github.com/sahilmgandhi/m152b-fall2018

CS M152B Codebase Fall 2018

c color-recognition gyroscope hdmi microblaze verilog xilinx-fpga

Last synced: 10 Jan 2025

https://github.com/yugr/gatecheck

Yet another Verilog static analyzer

clock-g gating static-analysis static-analyzer verilog

Last synced: 27 Dec 2024

https://github.com/yaxsomo/iris_cubesat

This Repository is dedicated to FPGA development of the IRIS CubeSat

aerospace cubesat fpga free-space-optical-communiucation satellite verilog vhdl vivado xilinx

Last synced: 11 Jan 2025

https://github.com/sinakarvandi/fpga

Random FPGA Projects

chisel3 fpga verilog vhdl vitis vivado zynq

Last synced: 18 Jan 2025

https://github.com/awrsha/logical-circuit-laboratory

verilog exercises for LC Lab at Qazvin islamic azad university

modelsim verilog

Last synced: 12 Jan 2025

https://github.com/jgroman/fpga-tangprimer25k-experiments

Learning digital design with Tang Primer 25K

fpga verilog

Last synced: 20 Jan 2025

https://github.com/muhammadtalhasami/sv_verilator

System verilog learning journey. Here in this repo you learn about how to write system verilog test bench using verilator tool a c++ test bench. Verilator is basically a 2 state tool .

system-verilog-testbench systemverilog testbench verification verilator- verilator-testbench verilog verilog-hdl

Last synced: 06 Nov 2024

https://github.com/chenqianhe/learnprofessionalbasiccoursesincomputerscience

Learn Professional Basic Courses in Computer Science计算机专业基础课程学习

assembly computer-network computer-science computer-system-structure cpp operating-system principle-of-computer-composition professional-basic-courses verilog

Last synced: 19 Jan 2025

https://github.com/yasnakateb/uartcommunication

☎️ UART Communication Implementation in Verilog HDL

icarus-verilog iverilog serial-communication uart uart-interface uart-protocol uart-verilog verilog

Last synced: 20 Jan 2025

https://github.com/risto97/cascade_classifier

Python, C, RTL implementation of Viola Jones cascade classifier, using pretrained model from opencv.

face-detection fpga object-detection pygears python verilog viola-jones

Last synced: 21 Dec 2024

https://github.com/algosup/2024-2025-project-1-fpga-team-2

fpga verilog

Last synced: 16 Jan 2025

https://github.com/algosup/2024-2025-project-1-fpga-team-3

First project of the year 2024-2025

fpga frogger game verilog vga

Last synced: 16 Jan 2025

https://github.com/aben20807/computer_organization

1052_計算機組織 COMPUTER ORGANIZATION

cache cpu datapath pipeline single-cycle verilog

Last synced: 16 Jan 2025

https://github.com/grachale/microarchitecture_risc-v_isa

Design of a Processor Microarchitecture Supporting a Chosen Subset of RISC-V ISA Instructions.

assembly isa microarchitecture risc-v verilog

Last synced: 13 Jan 2025

https://github.com/namberino/nam85

An 8085-based Computer

8085 computer-architecture digital-logic fpga verilog

Last synced: 20 Jan 2025

https://github.com/yvesemmanuel/introduction_verilog

digital systems

digital-systems verilog verilog-components verilog-project

Last synced: 16 Jan 2025

https://github.com/yvesemmanuel/microwave

second project - Digital System

digital-systems verilog verilog-components verilog-project

Last synced: 16 Jan 2025

https://github.com/algosup/2024-2025-project-1-fpga-team-4

Recreating the arcade game Frogger using FPGA and Verilog

fpga retrogaming school-project verilog

Last synced: 16 Jan 2025

https://github.com/ashkan-khd/conways-game-of-life-verilog

An easy approach for Conway's Game Of Life with Verilog HDL

conways-game-of-life conways-game-of-life-verilog game-of-life game-of-life-verilog testbench verilog verilog-game-of-life verilog-hdl

Last synced: 20 Dec 2024

https://github.com/kyori19/verilog-otp

VerilogHDL implementation of One-Time Password Algorithm (HOTP)

hotp onetimepassword systemverilog verilog verilog-hdl

Last synced: 18 Jan 2025

https://github.com/engineeringsoftware/hdlp

Code and data for "On the Naturalness of Hardware Descriptions" in ESEC/FSE'20

deep-learning hardware-description-language machine-learning naturalness pytorch systemverilog verilog vhdl

Last synced: 18 Nov 2024

https://github.com/z4yx/thinpad-controller-zynq

RTL project for the controller SoC on Thinpad

fpga verilog zynq

Last synced: 01 Dec 2024

https://github.com/samridhisainii/digitaldesign

These are the question of digital design lab from our subject digital design lab which were done in lab

digital-design verilog

Last synced: 29 Nov 2024

https://github.com/yahia3200/spi-protocol-implementation-using-verilog

Implementing SPI interface using Verilog

fpga spi verilog

Last synced: 21 Nov 2024

https://github.com/phillbush/tbgen

Testbench generator in AWK for Verilog modules

awk testbench testbench-generator testbench-generator-verilog verilog

Last synced: 22 Nov 2024

https://github.com/akhilrai28/alarm-clock

This project implements a fully functional digital alarm clock using Verilog and Vivado. The design includes features such as setting the time, alarm functionality, and real-time clock display. The project simulates clock timing and alarm triggers, with testbenches for verifying accuracy and reliability on FPGA.

alarm alarm-clock clock fpga hardware real-time simulation testbench verilog vivado

Last synced: 15 Dec 2024

https://github.com/alokmenghrajani/adventofcode2018

Advent of Code 2018. Solutions using Verilog + icestick fpga! ☃️🎄🎁🦌🎅

2018 advent-of-code-2018 advent-of-code-2018-fpga adventofcode adventofcode2018 fpga solutions upping-the-ante verilog

Last synced: 25 Nov 2024

https://github.com/pvgupta24/cse-labs

Dump for CSE Lab assignments and programs

algorithms c computer-architecture cpp data-structures mips opengl verilog

Last synced: 06 Jan 2025

https://github.com/niedzielski/swankmania

Graphics processor and ACX705AKM LCD driver hardware implementation and misc.

fpga game gpu hdl verilog

Last synced: 08 Dec 2024

https://github.com/byte-me404/jku-tt06-ps2-morse-encoder

Custom ASIC design which decodes a PS/2 keyboard, furthermore it encodes and outputs the data as morse code

asic ps2-keyboard tinytapeout verilog

Last synced: 05 Jan 2025

https://github.com/ehsanshahbazii/digital-vlsi-system-design-projects

سورس کد پروژه های درس طراحی سیستم های دیجیتال برنامه پذیر دانشگاه تبریز مقطع کارشناسی رشته مهندسی کامپیوتر

verilog verilog-code verilog-components verilog-project vlsi

Last synced: 10 Nov 2024

https://github.com/lebrancconvas/verilog-playground

Verilog Playground.

digital-electronics logic-gates verilog

Last synced: 08 Jan 2025

https://github.com/cpehle/cascade

Cycle based C++ hardware simulation infrastructure

hardware simulation verilog

Last synced: 15 Dec 2024

https://github.com/liu42/processor

《计算机组成原理》课程设计，基于 MIPS 的流水线 CPU 系统设计。

architecture computer-architecture course-project cpu fpga homework-project mips mips-architecture mips-processor pipeline verilog

Last synced: 21 Dec 2024

https://github.com/barrettotte/subarashii-cpu

A 16-bit RISC CPU inspired by MIPS. I designed this to learn more about computer architecture/organization.

cpu homebrew risc-processor verilog verilog-cpu

Last synced: 09 Dec 2024

https://github.com/hedhyw/simple-4bit-cpu

Vivado project with example of simple 4bit CPU

cpu mips verilog vivado xilinx

Last synced: 31 Dec 2024

https://github.com/ain1084/audio_echo_effect

Simple echo effect implementation with digital audio processing.

audio-processing i2s-audio lattice-fpga verilog

Last synced: 20 Dec 2024

https://github.com/shyamal-anadkat/the-11-of-us

adc ece551 flight-controller hdl integrator quadcopter synthesis system-verilog uart verilog vhdl

Last synced: 16 Dec 2024

https://github.com/amir78729/logical-circuits-course-final-project

My Logical Circuits course Final Project - Fall98(2019) - VERILOG

logical-circuits verilog

Last synced: 18 Jan 2025

https://github.com/ellisgl/addressable-debouncer-verilog

Addressable 8 SPDT debouncer in Verilog

cpld debounce debounce-button debouncing fpga verilog

Last synced: 19 Jan 2025

https://github.com/acmachado14/circuitoscombinacionais

Circuitos Combinacionais em Verilog | Trabalho pratico pra disciplina de Introdução aos Sistemas Lógicos - UFV

verilog

Last synced: 20 Nov 2024

https://github.com/rithwikksvr/verilog-snake-game

Last semester we made a Snake Game implemented on Hardware. For this Purpose we used Basys 2 Spartan-3E FPGA, 7x5 LED Matrix and Verilog Programming.

fpga verilog

Last synced: 12 Jan 2025