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Verilog
Verilog is a widely-used hardware description language (HDL) that enables designers to model, simulate, and synthesize digital circuits. It provides a text-based format for specifying the structure and behavior of electronic systems, making it easier to design complex hardware components such as microprocessors, memory, and communication devices.
- GitHub: https://github.com/topics/verilog
- Wikipedia: https://en.wikipedia.org/wiki/Verilog
- Aliases: hdl, hardware-description-language,
- Last updated: 2025-02-15 00:29:20 UTC
- JSON Representation
https://github.com/marialmeida1/study-ac
Atividades de Arquitetura de Computadores 1
arquitetura-de-computadores java python verilog
Last synced: 05 Jan 2025
https://github.com/abdallahabusidu/cmp305-introduction-verilog
introduction to Verilog in Integrated Circuit Design And VLSI technology
verilog verilog-code verilog-hdl verilog-project
Last synced: 06 Feb 2025
https://github.com/byte-me404/tt-ps2-morse-encoder
Custom ASIC design which decodes a PS/2 keyboard, furthermore it encodes and outputs the data as morse code
asic morse-code ps2-keyboard tinytapeout verilog
Last synced: 05 Jan 2025
https://github.com/ain1084/dual_clock_buffer
Dual clock buffer for modules connected by valid-ready protocol
Last synced: 13 Feb 2025
https://github.com/cmpark0126/mips_32bits
Implements 32bits MIPS with verilog. (18.11.25 ~ 18.12.)
Last synced: 15 Feb 2025
https://github.com/shuregg/riscv-simple-cpu
Creating a risc-v processor
cpu risc-v riscv riscv32 rtl systemverilog verification verilog verilog-hdl
Last synced: 06 Feb 2025
https://github.com/lemongrb/frequencydivider
verilog code for frequency divider circuit implemented with verilog hdl
digital-design fpga frequency-divider hardware-description-language hdl verilog
Last synced: 10 Jan 2025
https://github.com/lemongrb/sequencedetector
11001 sequence detector
asic digital-design fpga hardware hardware-description-language hdl sequence-detection sequence-detector verilog
Last synced: 10 Jan 2025
https://github.com/junzhengca/space-enemies
Rip off of space invaders coded in Verilog with VGA output support, intended for DE2-115 FPGA board. Final project for CSCB58.
assignment de2-115 hardware project verilog
Last synced: 06 Feb 2025
https://github.com/hiyouga/digic-experiment
BUAA CST Autumn 2018 Digital Circuit Experiment
Last synced: 14 Feb 2025
https://github.com/wpmed92/takerisc
A RISC-V RV32I Core written in TL-Verilog
hardware riscv riscv32 tl-verilog verilog
Last synced: 03 Feb 2025
https://github.com/tdjsnelling/garbled-circuits
Yao’s Garbled Circuits in TypeScript
cryptography garbled-circuits javascript mpc multiparty-computation nodejs oblivious-transfer typescript verilog
Last synced: 08 Feb 2025
https://github.com/the-pinbo/risc-spm
This project involves the development and enhancement of a RISC Stored-Program Machine (RISC SPM), based on the architecture detailed in "Advanced Digital Design with the Verilog HDL" by Michael D. Ciletti.
computer-architecture riscv verilog
Last synced: 16 Feb 2025
https://github.com/tmahlburg/mriscv
simple, modular rv32i implementation (WIP)
risc-v riscv riscv32 rv32i verilog verilog-hdl
Last synced: 17 Jan 2025
https://github.com/xilover/iot-and-edge-computing
Hands-on learning experience in IoT, edge computing, and embedded systems using a variety of platforms such as microcontrollers (nRF, STM32, ESP32), FPGAs (Xilinx), and SoCs (Raspberry Pi, Zynq).
aws-iot azure-iot ble circuit-design edge-computing esp32 fpga iot mqtt nrf pynq-z2 raspberry-pi rtos stm32 system-on-chip verilog vhdl vivado xilinx xilinx-zynq
Last synced: 18 Dec 2024
https://github.com/pavlostzitzos/hdls-intro
SystemVerilog , Verilog , Verilog-A , Verilog-AMS tutorial
verilog verilog-hdl verilog-testbenches vhdl
Last synced: 15 Feb 2025
https://github.com/xtrinch/icestick-fpga-example
Example project for Lattice icestick fpga
fpga icestorm-toolchain verilog
Last synced: 14 Feb 2025
https://github.com/bilalm04/combination-lock-fsm
Moore FSM combination lock in Verilog for DE1-SOC Board.
Last synced: 31 Dec 2024
https://github.com/sgq995/rc4-de0-nano-soc
It's a cryptoprocessor that implements de RC4 algorithm
de0-nano-soc fpga fpga-soc rc4 verilog
Last synced: 07 Jan 2025
https://github.com/abtinz/logic-circuits-final-project
Aut Logic Circuits Finall Project Fall 1400
Last synced: 12 Jan 2025
https://github.com/liu42/pipeline
《计算机组成原理》课程设计,基于 MIPS 系统的流水线 CPU 设计
architecture computer-architecture course-project cpu fpga homework-project mips mips-architecture mips-processor pipeline verilog
Last synced: 23 Nov 2024
https://github.com/youseftareq33/digital_buildcombinationalcircuit_2
Using Verilog HDL on Quartus application build combinational circuit
Last synced: 16 Feb 2025
https://github.com/niqzart/pylohd
High-level framework for simplification and systematization of processes in electronic design
converter hdl python thesis-project verilog
Last synced: 01 Feb 2025
https://github.com/ewdlop/verilog-notes
HDLBit-Pratice. https://hdlbits.01xz.net/wiki/Main_Page
combinational-logic finte-state-machine flip-flops sequential-logic verilog
Last synced: 27 Dec 2024
https://github.com/carlkidcrypto/digital-systems-engineering
A repo for ECE 440 (Digital Systems Engineering) class projects
systemverilog verilog xilinx-vivado zynq
Last synced: 09 Feb 2025
https://github.com/justin-marian/fsm-vending-machine
FSM vending machine, it dispenses products based on user input and provides change based on the money introduced.
fsm vending-machine-proplem verilog
Last synced: 27 Dec 2024
https://github.com/justin-marian/tiny-risc-v
Minimalist RISC-V with a five-stage pipeline. It serves as a platform for understanding processor design principles.
isa-architecture risc-v-architecture verilog
Last synced: 27 Dec 2024
https://github.com/akielaries/hwverif
Sandbox for exploring Hardware Verification
Last synced: 20 Jan 2025
https://github.com/davoodeh/verilog2hspice
Do some simple conversions on Verilog files to make them compatible with HSpice
Last synced: 08 Feb 2025
https://github.com/memgonzales/hdl-flip-flop
Compilation of Verilog behavioral models and test benches for the four types of flip-flops (SR, JK, D, and T)
behavioral-modeling computer-architecture flip-flop sequential-circuits verilog
Last synced: 20 Jan 2025
https://github.com/mssola/hdl
Playing around with Hardware Description Languages.
Last synced: 27 Jan 2025
https://github.com/kaushalmodi/nim-svvpi
Wrapper for SystemVerilog VPI headers sv_vpi_user.h and vpi_user.h
1364-2005 1800-2017 nim pli systemverilog verilog vpi
Last synced: 16 Jan 2025
https://github.com/elifgokpinar/microprocessor-design
Quartus Project
microprocessor quartus verilog
Last synced: 13 Jan 2025
https://github.com/qasimwani/karnaugh-map-batch-calculator
Calculates Multiple Karnaugh Maps at once using Selenium and custom built parser. The program then converts the Boolean Expressions into Dataflow Verilog (VHDL)
converts dataflow-verilog karnaugh-map karnaugh-map-solver karnaugh-maps selenium verilog web-scraping
Last synced: 27 Dec 2024
https://github.com/susiejojo/sobel_filter
Sobel filter for edge detection in images supporting parallel processing using Verilog on Xilinx ISE 13.4
hdl sobel-filter verilog xilinx-ise
Last synced: 09 Feb 2025
https://github.com/kassane/fpga_course
Testing conducted during verilog studies
Last synced: 13 Jan 2025
https://github.com/namberino/simple-uart
Simple UART implementation in FPGA
Last synced: 20 Jan 2025
https://github.com/aledpl5/rock-paper-scissors-circuit
Uni project about the game rock-paper-scissors
blif circuit datapath datapath-design finate-state-machine sis systemverilog verilog
Last synced: 05 Jan 2025
https://github.com/rpigor/tpsim
TPSim (Timing and Power Simulator) is a gate-level circuit simulator with timing and power estimation capabilities
eda power-analysis simulator timing-analysis verilog
Last synced: 06 Jan 2025
https://github.com/khushiisaxena/clap-switch---microphone-based-led-control
This Arduino project uses a microphone sensor to toggle an LED based on detected sound variations. The code reads sound levels and switches the LED on or off when significant changes are detected.
Last synced: 17 Feb 2025
https://github.com/mohamad-shosha/alu-verilog-proteus
This 4-bit ALU design project has been implemented as part of the [Computer Aided Design] in the university , where we applied Verilog for hardware design and Proteus for simulation.
Last synced: 28 Dec 2024
https://github.com/urish/tt06-spell
A minimal, stack-based programming language created for The Skull CTF
Last synced: 11 Jan 2025
https://github.com/mongshil553/digital-engineering-verilog-assignments
Sophomore 2021 1st Semester Digital Engineering Verilog Assignments
fpga-programming verilog xilinx-vivado
Last synced: 13 Jan 2025
https://github.com/niw/chisel_test
A simple Chisel test project for myself to learn Chisel and FPGA.
chisel3 fpga orangecrab scala tinyfpga verilog
Last synced: 06 Jan 2025
https://github.com/saifalomari99/fpga_projects_saifalomari
This Repository is to showcase Saif Alomari's FPGA projects. Includes 25 high-level FPGA projects in various HDLs.
Last synced: 28 Dec 2024
https://github.com/sofiavalos/verilog_ethernet_10g_mac
Bloques y bancos de pruebas MAC para Ethernet 10G.
Last synced: 06 Feb 2025
https://github.com/soham9284/smart-home-automation-system
The Smart Home Automation System is a comprehensive solution that integrates sensors, manual controls, and automated logic to manage lighting, temperature, security, and emergency responses efficiently.
fpga fpga-board verilog xilinx-vivado
Last synced: 02 Feb 2025
https://github.com/assem-elqersh/mips-processor-designs
Comprehensive repository containing Verilog implementations of MIPS processors. Includes both single-cycle and multi-cycle architectures, each in separate directories, with full simulation testbenches and modular design components for educational and development purposes.
computer-architecture educational hardware-designs mips mips-architecture processor-design simulation verilog
Last synced: 27 Jan 2025
https://github.com/cepdnaclk/e18-co502-rv32im-pipeline-implementation-group4
Single-cycle MIPS-like processor with a memory subsystem including a cache.
computer-architecture risc-v verilog
Last synced: 11 Jan 2025
https://github.com/cepdnaclk/e18-co502-rv32im-pipeline-implementation-group03
RV32IM Pipeline Processor
Last synced: 11 Jan 2025
https://github.com/a-bdellatif/digitaldesignwithverilog
Simple circuits designed with verilog
asic behavioural dataflow design digitalsystems fpga structural verilog verilog-code verilog-project verilogprojects
Last synced: 03 Feb 2025
https://github.com/isaaczhang4/mips-cpu
Verilog Implementation of a Pipelined MIPS Single Cycle CPU
cpu-simulator hardware hardware-simulation mips-architecture verilog
Last synced: 10 Feb 2025
https://github.com/ethanuppal/berkeley-hardfloat
Downstream hardfloat with custom patches
berkeley floating-point verilog
Last synced: 07 Feb 2025
https://github.com/risto97/socmake
Build system for RTL and SoC designs
cmake cpu hardware rtl simulation systemc systemonchip systemrdl verilog
Last synced: 21 Dec 2024
https://github.com/markmll/todaystart-a153
As-shipped demo for the Altera Cyclone TodayStart-A153 board. Requires Quartus-II 10.1 SP1 minimum.
Last synced: 13 Feb 2025
https://github.com/limpix31/tangmega138kpro-blink
fpga hardware-design hdl system-verilog verilog
Last synced: 07 Jan 2025
https://github.com/abdullahmaqbool22/arithmetic-logic-unit-alu
A final semester project for Digital Logic Data.
Last synced: 29 Dec 2024
https://github.com/mohammadmahdi-abdolhosseini/digital-logic-courses
Digital Systems 1 & 2 + Digital Systems Laboratory 1 + Digital Electronics Circuit +Microprocessor Based and Embedded Design courses projects
Last synced: 07 Jan 2025
https://github.com/eonu/fpga
Hardware implementations for basic digital circuit designs in Verilog with a Xilinx Artix-7 FPGA chip on a Digilent Basys 3 development board.
artix-7 basys3 circuits digital-design fpga hardware hardware-designs hdl simulation testbench verilog vivado
Last synced: 29 Dec 2024
https://github.com/woolseyworkshop/article-getting-started-with-the-tinyfpga-bx
Getting Started With The TinyFPGA BX Article Resources
electronics programming tinyfpga-bx verilog
Last synced: 29 Dec 2024
https://github.com/woolseyworkshop/article-creating-a-configurable-multifunction-logic-gate-in-verilog
Creating A Configurable Multifunction Logic Gate In Verilog Article Resources
Last synced: 29 Dec 2024
https://github.com/3-o-3/cod5
Public Domain (⊄) Computer on FPGA
fpga fpga-soc public-domain ternary ternary-computer verilog
Last synced: 11 Feb 2025
https://github.com/azazhassankhan/verilogutilitysuite
VerilogUtilitySuite 🚀 Welcome to our SystemVerilog playground! 🤖 Dive into the world of hardware description language (HDL) with our repository, where RTL designs meet creativity.
circuit component-architecture systemverilog verilog
Last synced: 21 Jan 2025
https://github.com/kitune-san/kf76489
KF76489 - 76489-like Digital Complex Sound generator written in SystemVerilog
fpga sn76489 systemverilog verilog
Last synced: 21 Jan 2025
https://github.com/kitune-san/kfmmc_v2
Multi media card access controller written in HDL
hdl mmc multimediacard sdc sdcard verilog verilog-hdl
Last synced: 21 Jan 2025
https://github.com/mohammadmahdi-abdolhosseini/computer-architecture-lab
Computer Architecture Lab - Assignments - Fall 2023
arm-processor fpga modelsim quartus2 systemverilog verilog vhdl
Last synced: 07 Jan 2025
https://github.com/roscibely/arithmetic-logic-unit
A simple arithmetic logic unit (ALU) with System verilog
Last synced: 21 Jan 2025
https://github.com/davidvarshanidze/cpu
CPU implementation in MIPS Assembly and Verilog
Last synced: 04 Feb 2025
https://github.com/rogerfan48/course-soph1-hdl
Materials and coursework for Hardware Design Lab (Sophomore Fall). Contains exercises, assignments, and laboratory work.
Last synced: 08 Jan 2025
https://github.com/coldnew/nand2tetris
My notes and impement on Nand2Tetris courses
coursearea nand2tetris personal-notes verilator verilog
Last synced: 15 Jan 2025
https://github.com/vlad-ivanov-name/verilog-zeroall
Resets all register to zero in a Verilog design
Last synced: 31 Jan 2025
https://github.com/pawel2000pl/verilogleddriver
Led RGB driver written in verilog, implemented for Mimas A7 Mini FPGA Development Board
fpga led-controller led-driver pwm pwm-driver systemverilog verilog vivado
Last synced: 22 Jan 2025
https://github.com/akafael/verilog-sandbox
selflearning tutorial-exercises verilog
Last synced: 28 Jan 2025
https://github.com/taffarel55/verilog
Documentação dos exemplos que fiz enquanto estudava a linguagem de descrição de hardware Verilog.
verilog verilog-examples verilog-hdl
Last synced: 09 Jan 2025
https://github.com/radinshahdaei/ce40223-dsd
Practical assignments and projects for "Digital Systems Design".
Last synced: 28 Jan 2025
https://github.com/kaleid-liner/fpga-tetris
Tetris based on Nexys4 DDR FPGA Board
Last synced: 16 Jan 2025
https://github.com/tanmayv25/microprocessor-system-design
Contains the lab work of Microprocessor System Design. All the FPGA prototyping, Drivers and OS modules.
fpga-soc linux-kernel-module sensor-devices verilog xilinx-vivado
Last synced: 30 Dec 2024
https://github.com/ilovebacteria/elevator-state-machine
My Digital Logic course project - Elevator state machine
digital-logic moore-machine state-machine verilog
Last synced: 14 Nov 2024
https://github.com/shishir-dey/pcb-dev-fpga-ice40
A 2 layer development board with a Lattice Semiconductor ICE40UP5K-SG48ITR FPGA. Made with KiCad
development-board fpga hardware pcb-design verilog
Last synced: 14 Jan 2025