https://github.com/rambodrahmani/dalle_porte_and_or_not_al_sistema_calcolatore

Dalle Porte AND OR NOT Al Sistema Calcolatore. Un viaggio nel mondo delle reti logiche in campagnia del linguaggio Verilog.

altera boolean-algebra boolean-logic logic-gates modelsim verilog

Last synced: 29 Dec 2024

https://github.com/kkkaan/metu-ceng-thes

Some of the homeworks I have done at metu ceng.

bash c clingo cpp haskell java prolog python quantum-computing verilog

Last synced: 04 Jan 2025

https://github.com/drom/vpreproc

Verilog preprocessor bindings for Node.js

napi nodejs preprocessor verilog

Last synced: 10 Feb 2025

https://github.com/weisrc/fpgaudio

MIDI file to Verilog Code Generation - FPGAudio!

midi verilog

Last synced: 23 Dec 2024

https://github.com/ellisgl/driver-yl-3

Verilog code to run the YL-3 8 digit 7 segment display.

seven-segment verilog

Last synced: 19 Jan 2025

https://github.com/delhatch/flipdot_video

Video streaming from a camera to a 58x24 pixel flipdot display. See the two flipdot_display*.mp4 videos. All processing in Verilog RTL (no softcore uP).

altera de2-115 flipdot flipdots fpga verilog

Last synced: 13 Jan 2025

https://github.com/cmpark0126/mips_32bits

Implements 32bits MIPS with verilog. (18.11.25 ~ 18.12.)

fpga mips32cpu verilog

Last synced: 23 Dec 2024

https://github.com/a-bdellatif/sequencedetector

11001 sequence detector

asic digital-design fpga hardware hardware-description-language hdl sequence-detection sequence-detector verilog

Last synced: 03 Feb 2025

https://github.com/shuregg/riscv-simple-cpu

Creating a risc-v processor

cpu risc-v riscv riscv32 rtl systemverilog verification verilog verilog-hdl

Last synced: 06 Feb 2025

https://github.com/yasnakateb/sdramcontroller

🛠 A SDRAM controller in Verilog HDL

icarus-verilog iverilog memory-controller sdram sdram-controller verilog verilog-hdl

Last synced: 20 Jan 2025

https://github.com/francoriba/alu-uart-basys3

UART modules interface using Verilog for the Basys3 board (Digilent). Computer Architecture 2023. FCEFyN, UNC, Argentina

arquitectura-de-computadores basys3-fpga computerarchitecture fcefyn hardwaredescription uart unc verilog

Last synced: 11 Jan 2025

https://github.com/calint/zen-x

experimental retro 16 bit cpu written in verilog xilinx vivado intended for fpga Cmod S7 from Digilent

16-bit cmod-s7 cpu fpga verilog vintage vivado xilinx

Last synced: 10 Jan 2025

https://github.com/hiyouga/digic-experiment

BUAA CST Autumn 2018 Digital Circuit Experiment

digital-circuit verilog

Last synced: 05 Jan 2025

https://github.com/mummanajagadeesh/i2c-protocol-verilog

Verilog Implementation of I2C Protocol using Finite State Machine (FSM) design

finite-state-machine fpga fsm i2c i2cprotocol verilog verilog-hdl verilog-project xilinx xilinx-vivado

Last synced: 25 Jan 2025

https://github.com/kar-dim/icsd-digitalsystems

Some Verilog projects, implemented as part of my university coursework (2013-2019, Information and Communications Systems Engineering, University of the Aegean).

verilog

Last synced: 04 Jan 2025

https://github.com/chayashri2308/parking_management

Parking Management System using Verilog, to identify the occupied and vacant space in a parking lot.

fpga verilog

Last synced: 31 Jan 2025

https://github.com/chayashri2308/vending_machine

A simple Vending Machine design for only one product using Verilog. The user can enter three different currency notes and based on the price of the product, the machine dispenses the product and gives the change.

verilog

Last synced: 31 Jan 2025

https://github.com/marceldobehere/goofy-cpu-verilog

cpu cpu-simulator goofy goofy-cpu sim verilog

Last synced: 04 Jan 2025

https://github.com/peplxx/morse-coder

This project was made for optional fpga project during F23 Computer Architecture course. This is Quartus Project for turning fpga board into morse coder.

fpga-board fpga-programming morse-code quartus-prime verilog

Last synced: 13 Feb 2025

https://github.com/alyssonmach/sistema-seguranca-residencial

Projeto final da disciplina Laboratório de Circuitos Lógicos - Sistema de Segurança Residencial.

logic-circuit logic-gates logisim project ufcg verilog

Last synced: 24 Dec 2024

https://github.com/ghazaleze/microblaze-equation-solver

for solving cubic equation

c fpga verilog

Last synced: 05 Jan 2025

https://github.com/ellisgl/addressable-debouncer-verilog

Addressable 8 SPDT debouncer in Verilog

cpld debounce debounce-button debouncing fpga verilog

Last synced: 19 Jan 2025

https://github.com/acmachado14/circuitoscombinacionais

Circuitos Combinacionais em Verilog | Trabalho pratico pra disciplina de Introdução aos Sistemas Lógicos - UFV

verilog

Last synced: 21 Jan 2025

https://github.com/adolbyb/vhdl-fpga-nexys-a7

A collection of code from CDA 4240C: Design of Digital System and Lab

artix-7 fpga hardware-description-language hdl nexys-a7 verilog vhdl xilinx-vivado

Last synced: 20 Jan 2025

https://github.com/justin-marian/fsm-vending-machine

FSM vending machine, it dispenses products based on user input and provides change based on the money introduced.

fsm vending-machine-proplem verilog

Last synced: 27 Dec 2024

https://github.com/a-bdellatif/digitaldesignwithverilog

Simple circuits designed with verilog

asic behavioural dataflow design digitalsystems fpga structural verilog verilog-code verilog-project verilogprojects

Last synced: 03 Feb 2025

https://github.com/vlad-ivanov-name/verilog-zeroall

Resets all register to zero in a Verilog design

modelsim verilog

Last synced: 31 Jan 2025

https://github.com/pawel2000pl/verilogleddriver

Led RGB driver written in verilog, implemented for Mimas A7 Mini FPGA Development Board

fpga led-controller led-driver pwm pwm-driver systemverilog verilog vivado

Last synced: 22 Jan 2025

https://github.com/akafael/verilog-sandbox

selflearning tutorial-exercises verilog

Last synced: 28 Jan 2025

https://github.com/taffarel55/verilog

Documentação dos exemplos que fiz enquanto estudava a linguagem de descrição de hardware Verilog.

verilog verilog-examples verilog-hdl

Last synced: 09 Jan 2025

https://github.com/sunzey/cpu_project

recording codes of CPU under mips ISA in lecture of computer organization

buaa buaa-co cpu learning verilog

Last synced: 16 Jan 2025

https://github.com/rinminase/cpe512

verilog

Last synced: 27 Dec 2024

https://github.com/toruniina/brainfxck-circuit

run brainfxck on FPGA

brainfuck verilog

Last synced: 03 Feb 2025

https://github.com/radinshahdaei/ce40223-dsd

Practical assignments and projects for "Digital Systems Design".

verilog

Last synced: 28 Jan 2025

https://github.com/rogerfan48/course-soph1-hdl

Materials and coursework for Hardware Design Lab (Sophomore Fall). Contains exercises, assignments, and laboratory work.

verilog vivado

Last synced: 08 Jan 2025

https://github.com/kaleid-liner/fpga-tetris

Tetris based on Nexys4 DDR FPGA Board

fpga tetris verilog

Last synced: 16 Jan 2025

https://github.com/tanmayv25/microprocessor-system-design

Contains the lab work of Microprocessor System Design. All the FPGA prototyping, Drivers and OS modules.

fpga-soc linux-kernel-module sensor-devices verilog xilinx-vivado

Last synced: 30 Dec 2024

https://github.com/jminjares4/digital-system-2

Digital System 2 Lab

digital-design verilog

Last synced: 10 Jan 2025

https://github.com/cepdnaclk/e18-co502-rv32im-pipeline-implementation-group03

RV32IM Pipeline Processor

risc-v verilog

Last synced: 11 Jan 2025

https://github.com/davidvarshanidze/cpu

CPU implementation in MIPS Assembly and Verilog

cpu mips-assembly verilog

Last synced: 04 Feb 2025

https://github.com/isaaczhang4/mips-cpu

Verilog Implementation of a Pipelined MIPS Single Cycle CPU

cpu-simulator hardware hardware-simulation mips-architecture verilog

Last synced: 10 Feb 2025

https://github.com/prinuvinod/digital-lab

These are some Verilog Programs

digital verilog

Last synced: 06 Jan 2025

https://github.com/ilovebacteria/elevator-state-machine

My Digital Logic course project - Elevator state machine

digital-logic moore-machine state-machine verilog

Last synced: 14 Nov 2024

https://github.com/shishir-dey/pcb-dev-fpga-ice40

A 2 layer development board with a Lattice Semiconductor ICE40UP5K-SG48ITR FPGA. Made with KiCad

development-board fpga hardware pcb-design verilog

Last synced: 14 Jan 2025

https://github.com/cepdnaclk/e18-co502-rv32im-pipeline-implementation-group4

Single-cycle MIPS-like processor with a memory subsystem including a cache.

computer-architecture risc-v verilog

Last synced: 11 Jan 2025

https://github.com/samiyaalizaidi/pipelined-risc-v-processor

A Pipelined RISC-V Processor with forwarding support and hazard detection.

assembly computer-architecture pipelining processor processor-architecture risc-v verilog vivado

Last synced: 16 Jan 2025

https://github.com/samiyaalizaidi/fpga

Verilog implementation of the basic structure of an FPGA

digital-system-design fpga verilog vivado

Last synced: 16 Jan 2025

https://github.com/ranitmanik/cs-verilog-assignments

A collection of Verilog code snippets and assignments for computer science coursework.

assignment coding iverilog low-level-programming practice practice-programming verilog

Last synced: 28 Jan 2025

https://github.com/assem-elqersh/mips-processor-designs

Comprehensive repository containing Verilog implementations of MIPS processors. Includes both single-cycle and multi-cycle architectures, each in separate directories, with full simulation testbenches and modular design components for educational and development purposes.

computer-architecture educational hardware-designs mips mips-architecture processor-design simulation verilog

Last synced: 27 Jan 2025

https://github.com/shiro-raven/verilog-mips

A verilog-based MIPS processor with pipelining

assembly mips mips-architecture verilog

Last synced: 01 Feb 2025

https://github.com/theoplayz2/eda-explorer

Инструмент на Python для разведочного анализа данных (EDA) и визуализации, поддерживающий загрузку данных CSV и JSON, с модульной архитектурой ООП. Практическая работа по теме: "Обнаружение и визуализация данных для понимания их сущности" дисциплины "МДК 13.01: Основы применения методов искусственного интеллекта в программировании".

analysis battery-life cqrs csharp data-analysis eeg-analysis exploratorydataanalysis json-visualization matplotlib messaging profile-report python verilog visualization

Last synced: 28 Jan 2025

https://github.com/jjateen/snake-game-verilog

This repository showcases a Verilog-based Snake and Apple Game, developed for the ECL 106: Digital System Design with HDL course. Running on an Altera DE10-Lite FPGA board and displayed on a VGA monitor, players control a snake to collect apples while avoiding obstacles. The snake grows longer with each apple, making the game progressively harder.

altera-fpga de10-lite fpga quartus-prime verilog verilog-project

Last synced: 17 Jan 2025

https://github.com/mthszr/stopwatch-verilog

Projeto da 2ª unidade, para a disciplina de Sistemas Digitais, no qual consiste em desenvolver um Cronômetro Digital, utilizando Verilog com a base de Máquina de Estados Finitos.

verilog verilog-hdl

Last synced: 22 Jan 2025

https://github.com/sea-n/nctu-108b-dcd

108 Spring - Digital Circuit Design

homework nctu verilog

Last synced: 07 Jan 2025

https://github.com/wassimhedfi/fpga_adc_pwm_motorcontrol

This repository contains the implementation of a motor speed control system using an FPGA. The speed is adjusted dynamically through a potentiometer, leveraging ADC for analog-to-digital conversion and PWM for precise motor control.

adc de10-lite fpga html motor-speed pwm verilog vhdl

Last synced: 31 Jan 2025

https://github.com/woolseyworkshop/article-getting-started-with-the-tinyfpga-bx

Getting Started With The TinyFPGA BX Article Resources

electronics programming tinyfpga-bx verilog

Last synced: 29 Dec 2024

https://github.com/soham9284/smart-home-automation-system

The Smart Home Automation System is a comprehensive solution that integrates sensors, manual controls, and automated logic to manage lighting, temperature, security, and emergency responses efficiently.

fpga fpga-board verilog xilinx-vivado

Last synced: 02 Feb 2025

https://github.com/caite21/cpu-core

16-bit CPU Core Design in Verilog

cpu verilog xilinx-vivado

Last synced: 22 Jan 2025

https://github.com/roscibely/arithmetic-logic-unit

A simple arithmetic logic unit (ALU) with System verilog

alu arithmetic verilog vhdl

Last synced: 21 Jan 2025

https://github.com/sofiavalos/verilog_ethernet_10g_mac

Bloques y bancos de pruebas MAC para Ethernet 10G.

ethernet mac verilog

Last synced: 06 Feb 2025

https://github.com/mohammadmahdi-abdolhosseini/computer-architecture-lab

Computer Architecture Lab - Assignments - Fall 2023

arm-processor fpga modelsim quartus2 systemverilog verilog vhdl

Last synced: 07 Jan 2025

https://github.com/saifalomari99/fpga_projects_saifalomari

This Repository is to showcase Saif Alomari's FPGA projects. Includes 25 high-level FPGA projects in various HDLs.

fpga systemverilog verilog

Last synced: 28 Dec 2024

https://github.com/niw/chisel_test

A simple Chisel test project for myself to learn Chisel and FPGA.

chisel3 fpga orangecrab scala tinyfpga verilog

Last synced: 06 Jan 2025

https://github.com/ethanuppal/berkeley-hardfloat

Downstream hardfloat with custom patches

berkeley floating-point verilog

Last synced: 07 Feb 2025

https://github.com/tanuj-maheshwari/fpga

Configurable FPGA Fabric simulated in Verilog

fpga verilog

Last synced: 23 Jan 2025

https://github.com/javiidiazglez/ec

Estructuras de Computadores

verilog

Last synced: 01 Jan 2025

https://github.com/mongshil553/digital-engineering-verilog-assignments

Sophomore 2021 1st Semester Digital Engineering Verilog Assignments

fpga-programming verilog xilinx-vivado

Last synced: 13 Jan 2025

https://github.com/urish/tt06-spell

A minimal, stack-based programming language created for The Skull CTF

tinytapeout verilog wizardry

Last synced: 11 Jan 2025

https://github.com/mohamad-shosha/alu-verilog-proteus

This 4-bit ALU design project has been implemented as part of the [Computer Aided Design] in the university , where we applied Verilog for hardware design and Proteus for simulation.

proteus verilog

Last synced: 28 Dec 2024

https://github.com/mosure/ece552-project-fall-2018

ece552 uw-madison verilog

Last synced: 27 Jan 2025

https://github.com/j-m-li/logical16x16

Hardware Description Language for EPROM and FLASH memories

eprom public-domain verilog

Last synced: 18 Nov 2024

https://github.com/andrejchoo/cpldctrum

ZX Spectrum clone on CPLD

cpld divmmc verilog zx-spectrum

Last synced: 05 Feb 2025

https://github.com/jackson-nestelroad/verilog-mips-processor

Single-cycle 32-bit MIPS processor implemented in SystemVerilog.

cpu mips processor verilog

Last synced: 29 Jan 2025

https://github.com/polaris000/cs_f342

Lab assignments and some practise done for the Computer Architecture course at BITS Pilani

assembly bits-pilani comparch computer-architecture labs practise verilog

Last synced: 09 Jan 2025

https://github.com/rpigor/tpsim

TPSim (Timing and Power Simulator) is a gate-level circuit simulator with timing and power estimation capabilities

eda power-analysis simulator timing-analysis verilog

Last synced: 06 Jan 2025

https://github.com/cr0a3/hardwarelib

A libary to create asics in short time

asic hardware verilog

Last synced: 23 Jan 2025

https://github.com/paulchen2713/introduction_to_veriloghdl

Digital System Design Course Practices

verilog

Last synced: 23 Jan 2025

https://github.com/kitune-san/kfmmc_v2

Multi media card access controller written in HDL

hdl mmc multimediacard sdc sdcard verilog verilog-hdl

Last synced: 21 Jan 2025

https://github.com/aledpl5/rock-paper-scissors-circuit

Uni project about the game rock-paper-scissors

blif circuit datapath datapath-design finate-state-machine sis systemverilog verilog

Last synced: 05 Jan 2025

https://github.com/kitune-san/kf76489

KF76489 - 76489-like Digital Complex Sound generator written in SystemVerilog

fpga sn76489 systemverilog verilog

Last synced: 21 Jan 2025

https://github.com/28ritu/alu

An ALU Design in Verilog

alu verilog waveform

Last synced: 22 Dec 2024

https://github.com/madh93/scpu

Simple 16-bit CPU written in Verilog.

cpu datapath verilog

Last synced: 29 Jan 2025

https://github.com/gcerpa01/compe470

Work of my projects I worked on while enrolled in SDSU's COMPE470 Digital Circuits course in Spring 2023

verilog verilog-hdl vivado

Last synced: 17 Jan 2025

https://github.com/arsham-lh/computer-architecture

Code files related to the Computer Architecture course, taught by M. Movahedin

computer-architecture mips-assembly multi-cycle-processor single-cycle-processor verilog

Last synced: 17 Jan 2025

https://github.com/arsham-lh/logic-circuits

Simulation of logic circuits using Verilog, Proteus and other tools.

digital-circuits fsm logic-circuits mealy-machine moore-machine proteus verilog

Last synced: 17 Jan 2025

https://github.com/azazhassankhan/verilogutilitysuite

VerilogUtilitySuite 🚀 Welcome to our SystemVerilog playground! 🤖 Dive into the world of hardware description language (HDL) with our repository, where RTL designs meet creativity.

circuit component-architecture systemverilog verilog

Last synced: 21 Jan 2025

https://github.com/abdullahmaqbool22/arithmetic-logic-unit-alu

A final semester project for Digital Logic Data.

dld dld-project verilog

Last synced: 29 Dec 2024

https://github.com/tdholmes/digitaldesign-pong

Verilog Pong game designed for Digital Design in December of 2013.

pong verilog

Last synced: 29 Jan 2025

https://github.com/mark-mdo47/fpga_rbg_2_rbgw

Lattice iCE40 FPGA convert WS2812b RGB from ESP32 to SK6812 RGBW

apio esp32-arduino fpga ice40 icestick led sk6812 verilog ws2812b

Last synced: 22 Jan 2025

https://github.com/avantikaadiyodi/fpga-based-fault-analyzer-for-industrial-motors

cpp dsp fft fpga instrumentation matlab motor verilog

Last synced: 09 Feb 2025

https://github.com/risto97/socmake

Build system for RTL and SoC designs

cmake cpu hardware rtl simulation systemc systemonchip systemrdl verilog

Last synced: 21 Dec 2024

https://github.com/skpro-glitch/riscv-processor-asic

This is a basic RISC-V based processor under development. It follows the 32-bit Integer ISA.

asic asic-design asic-verification fpga hardware-designs open-source openlane openlane-flow processor-architecture processor-design risc-v riscv32 verilog verilog-hdl vlsi vlsi-design

Last synced: 13 Feb 2025

https://github.com/peplxx/keyboard-driver-vhdl

Driver for handling matrix keyboard 4x4 on FPGA Board

driver fpga fpga-programming hardware keyboard verilog verilog-hdl

Last synced: 13 Feb 2025

https://github.com/namberino/simple-uart

Simple UART implementation in FPGA

fpga uart verilog

Last synced: 20 Jan 2025

https://github.com/markmll/todaystart-a153

As-shipped demo for the Altera Cyclone TodayStart-A153 board. Requires Quartus-II 10.1 SP1 minimum.

fpga verilog vhdl

Last synced: 21 Dec 2024

https://github.com/centuriontheman/efficientmodulooperations

The project implements a high-performance modulo algorithm.

modulo modulo-arithmetics python university university-project verilog

Last synced: 05 Feb 2025

https://github.com/kassane/fpga_course

Testing conducted during verilog studies

fpga verilog

Last synced: 13 Jan 2025

https://github.com/idorobots/upduino-blinky

Two simple Upduino projects that blink an RGB LED in various ways.

blinky fpga ice40 ice40up5k led upduino upduino-board verilog

Last synced: 13 Feb 2025

https://github.com/abstractmachines/verilog-shift-register

A shift register in Verilog. Bidirectional pin use.

embedded-systems hardware shift-register verilog

Last synced: 06 Feb 2025

https://github.com/aliiiw/computer-architecture-lab

Implement Mips cpu with Verilog

forwarding mips pipeline verilog

Last synced: 30 Jan 2025