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Verilog

Verilog is a widely-used hardware description language (HDL) that enables designers to model, simulate, and synthesize digital circuits. It provides a text-based format for specifying the structure and behavior of electronic systems, making it easier to design complex hardware components such as microprocessors, memory, and communication devices.

https://github.com/jn513/baby-risco-5

Multi-cycle RISC-V processor with RV32E implementation

riscv riscv32 riscv32e verilog verilog-hdl

Last synced: 15 Dec 2024

https://github.com/jn513/estudos_verilog

Exemplos feito em verilog para estudos

fpga fpga-programming hardware verilog verilog-code verilog-hdl

Last synced: 15 Dec 2024

https://github.com/rambodrahmani/dalle_porte_and_or_not_al_sistema_calcolatore

Dalle Porte AND OR NOT Al Sistema Calcolatore. Un viaggio nel mondo delle reti logiche in campagnia del linguaggio Verilog.

altera boolean-algebra boolean-logic logic-gates modelsim verilog

Last synced: 29 Dec 2024

https://github.com/mat1g3r/csc258_final_project

CSC258 final project

verilog

Last synced: 22 Nov 2024

https://github.com/asankasovis/eight_bit_computer

🎛️ FPGAs are an interesting invention that is expected to revolutionize the digital industry. This series will focus on building the 8-bit computer that Ben Eater built on his youtube channel. However, it will be done not with actual chips and hardware, but with Verilog code and FPGA simulations.

8bit beneater computer fpga fpga-programming verilog

Last synced: 08 Dec 2024

https://github.com/rauhul/ece385

Digital Systems Laboratory UIUC FA 2016

altera fpga quartus-prime systemverilog verilog

Last synced: 02 Dec 2024

https://github.com/abdallahabusedo/cmp305-introduction-verilog

introduction to Verilog in Integrated Circuit Design And VLSI technology

verilog verilog-code verilog-hdl verilog-project

Last synced: 13 Dec 2024

https://github.com/tomarus/midirouter

CMOD-A7 FPGA MIDI Merger/Router/Switch.

fpga midi verilog

Last synced: 15 Dec 2024

https://github.com/ain1084/dual_clock_buffer

Dual clock buffer for modules connected by valid-ready protocol

protocol-buffers verilog

Last synced: 20 Dec 2024

https://github.com/ain1084/serial_audio_encoder

Serial audio encoder

encoder i2s-audio verilog

Last synced: 20 Dec 2024

https://github.com/sauravmaheshkar/verilog-template

❄️ Template for Verilog Projects using iverilog and gtkwave (nix devShell supported)

hardware-description-language template-project verilog verilog-template vhdl

Last synced: 06 Dec 2024

https://github.com/eshansurendra/uart-fpga

This repository documents a project undertaken as part of the EN2111 Electronic Circuit Design module at the University of Moratuwa, focusing on the implementation of a UART communication link between two FPGA boards.

digital-design embedded-systems fpga quartus-prime systemverilog-hdl testbench uart verilog

Last synced: 17 Nov 2024

https://github.com/kareimgazer/pci_target_device

Verilog simulation for a Target Device on a PCI bus with read and write transactions.

pci pci-devices verilog xilin xilinx-vivado

Last synced: 08 Dec 2024

https://github.com/cmpark0126/mips_32bits

Implements 32bits MIPS with verilog. (18.11.25 ~ 18.12.)

fpga mips32cpu verilog

Last synced: 23 Dec 2024

https://github.com/vincent-g-van/one-time-pad-fpga

64-Bits One-Time Pad on FPGA Board (Nexys 4 DDR Artix-7).

diligent nexys4 one-time-pad otp seven-segment verilog vivado

Last synced: 03 Dec 2024

https://github.com/manighazaee/cpu

CPU architecture implemented in Verilog and its assembler in Rust.

architecture assembler cpu rust verilog

Last synced: 03 Dec 2024

https://github.com/tmahlburg/mriscv

simple, modular rv32i implementation (WIP)

risc-v riscv riscv32 rv32i verilog verilog-hdl

Last synced: 16 Nov 2024

https://github.com/chayashri2308/parking_management

Parking Management System using Verilog, to identify the occupied and vacant space in a parking lot.

fpga verilog

Last synced: 04 Dec 2024

https://github.com/chayashri2308/vending_machine

A simple Vending Machine design for only one product using Verilog. The user can enter three different currency notes and based on the price of the product, the machine dispenses the product and gives the change.

verilog

Last synced: 04 Dec 2024

https://github.com/wpmed92/takerisc

A RISC-V RV32I Core written in TL-Verilog

hardware riscv riscv32 tl-verilog verilog

Last synced: 09 Dec 2024

https://github.com/dineshpinto/timetagger

FPGA programming for nanosecond photon counting

c fpga fpga-programming linux photonics picosecond swig-binding verilog

Last synced: 09 Dec 2024

https://github.com/dineshpinto/stm32f4

Combining an FPGA, micro-controller and AWG for nanosecond photon counting

assembly awg c microcontroller photonics verilog

Last synced: 09 Dec 2024

https://github.com/bilalm04/combination-lock-fsm

Moore FSM combination lock in Verilog for DE1-SOC Board.

de1-soc hardware verilog

Last synced: 31 Dec 2024

https://github.com/andrejchoo/uart_spiflash_programmer_on_fpga

UART programmer SPI FLASH 25-series on FPGA or CPLD

fpga programmer spi-flash verilog

Last synced: 11 Dec 2024

https://github.com/pseudoincorrect/fpga_mcu_wifi

Link between a PC and a FPGA through wifi

c fpga socket verilog wifi

Last synced: 16 Dec 2024

https://github.com/rishabh-agarwal/cisc530-computersystemarchitecture

This repository contain HW and assignment for ComputerSystemArchitecture class at Harrisburg University

assignment cisc530 harrisburg homework kapila university verilog

Last synced: 28 Dec 2024

https://github.com/junzhengca/space-enemies

Rip off of space invaders coded in Verilog with VGA output support, intended for DE2-115 FPGA board. Final project for CSCB58.

assignment de2-115 hardware project verilog

Last synced: 13 Dec 2024

https://github.com/drom/vpreproc

Verilog preprocessor bindings for Node.js

napi nodejs preprocessor verilog

Last synced: 18 Dec 2024

https://github.com/weisrc/fpgaudio

MIDI file to Verilog Code Generation - FPGAudio!

midi verilog

Last synced: 23 Dec 2024

https://github.com/jgroman/fpga-tangprimer25k-experiments

Learning digital design with Tang Primer 25K

fpga verilog

Last synced: 19 Nov 2024

https://github.com/pavlostzitzos/hdls-intro

SystemVerilog , Verilog , Verilog-A , Verilog-AMS tutorial

verilog verilog-hdl verilog-testbenches vhdl

Last synced: 24 Dec 2024

https://github.com/marialmeida1/study-ac

Atividades de Arquitetura de Computadores 1

arquitetura-de-computadores java python verilog

Last synced: 05 Jan 2025

https://github.com/xilover/iot-and-edge-computing

Hands-on learning experience in IoT, edge computing, and embedded systems using a variety of platforms such as microcontrollers (nRF, STM32, ESP32), FPGAs (Xilinx), and SoCs (Raspberry Pi, Zynq).

aws-iot azure-iot ble circuit-design edge-computing esp32 fpga iot mqtt nrf pynq-z2 raspberry-pi rtos stm32 system-on-chip verilog vhdl vivado xilinx xilinx-zynq

Last synced: 18 Dec 2024

https://github.com/alyssonmach/sistema-seguranca-residencial

Projeto final da disciplina Laboratório de Circuitos Lógicos - Sistema de Segurança Residencial.

logic-circuit logic-gates logisim project ufcg verilog

Last synced: 24 Dec 2024

https://github.com/ghazaleze/microblaze-equation-solver

for solving cubic equation

c fpga verilog

Last synced: 05 Jan 2025

https://github.com/calint/zen-x

experimental retro 16 bit cpu written in verilog xilinx vivado intended for fpga Cmod S7 from Digilent

16-bit cmod-s7 cpu fpga verilog vintage vivado xilinx

Last synced: 10 Jan 2025

https://github.com/sameer/de2-115-template

HDLMake template for terasIC DE2-115

de2-115 hdlmake template verilog vhdl

Last synced: 18 Dec 2024

https://github.com/byte-me404/tt-ps2-morse-encoder

Custom ASIC design which decodes a PS/2 keyboard, furthermore it encodes and outputs the data as morse code

asic morse-code ps2-keyboard tinytapeout verilog

Last synced: 05 Jan 2025

https://github.com/tm90/verilogmodules

generic Verilog modules for reuse...

generic-verilog-modules systemverilog verilog

Last synced: 13 Nov 2024

https://github.com/kar-dim/icsd-digitalsystems

Some Verilog projects, implemented as part of my university coursework (2013-2019, Information and Communications Systems Engineering, University of the Aegean).

verilog

Last synced: 04 Jan 2025

https://github.com/muhammadtalhasami/rtl_practice

This repository contain basic verilog codes which include the implementation of DLD (digital logic desgin ) circuits.

100daysofrtl hardware-coding muhammadtalhasami-github- rtl testbench verilog verilog-practice vhdl

Last synced: 25 Dec 2024

https://github.com/the-pinbo/risc-spm

This project involves the development and enhancement of a RISC Stored-Program Machine (RISC SPM), based on the architecture detailed in "Advanced Digital Design with the Verilog HDL" by Michael D. Ciletti.

computer-architecture riscv verilog

Last synced: 25 Dec 2024

https://github.com/sofiavalos/verilog_ethernet_10g_pcs

Bloques y bancos de pruebas PCS para Ethernet 10G.

ethernet pcs verilog

Last synced: 05 Jan 2025

https://github.com/hiyouga/digic-experiment

BUAA CST Autumn 2018 Digital Circuit Experiment

digital-circuit verilog

Last synced: 05 Jan 2025

https://github.com/vgalovic/hdl_examples

A collection of VHDL and Verilog examples organized by language and practice section, with setup.tcl files for easy Vivado setup. These examples reflect my FPGA development practice and learning.

tcl verilog vhdl vivado

Last synced: 03 Jan 2025

https://github.com/m13253/sbmips

Naïve MIPS32-like CPU design with pipeline on a Xilinx FPGA

fpga mips mips32 verilog

Last synced: 05 Dec 2024

https://github.com/bucknalla/axis-interfacer

Extract AXI (Full, Lite and Stream) interfaces from Verilog source files

axi axi-lite axis verilog xilinx

Last synced: 09 Jan 2025

https://github.com/bucknalla/warc_fusesoc

WARC Open Fusesoc Cores Repository

hls ip migen open-cores verilog

Last synced: 09 Jan 2025

https://github.com/vitalyankh/open-fpga-tutorial

Open FPGA Tutorial

chisel fpga verilog

Last synced: 12 Nov 2024

https://github.com/yaxsomo/iris_cubesat

This Repository is dedicated to FPGA development of the IRIS CubeSat

aerospace cubesat fpga free-space-optical-communiucation satellite verilog vhdl vivado xilinx

Last synced: 12 Nov 2024

https://github.com/arsham-lh/logic-circuits

Simulation of logic circuits using Verilog, Proteus and other tools.

digital-circuits fsm logic-circuits mealy-machine moore-machine proteus verilog

Last synced: 16 Nov 2024

https://github.com/ain1084/machxo2_serial_to_spdif_transmitter

Serial (LPCM) to S/PDIF transmitter. Using MachXO2 (1200HC QFN32).

audio machxo2 spdif verilog

Last synced: 20 Dec 2024

https://github.com/calint/znxcr

experimental retro 16 bit cpu written in verilog xilinx vivado intended for fpga Cmod S7 from Digilent

16-bit cmod-s7 cpu fpga verilog

Last synced: 10 Jan 2025

https://github.com/rejunity/atari-2600-fpga

Continue development of Atari 2600 in Verilog. Based on the original work by Daniel Beer.

atari-2600 atari2600 fpga retrogaming verilog

Last synced: 24 Nov 2024

https://github.com/daulpavid/verilog_template

Boilerplate project template for verilog that includes directories for simulation, documentation, and formal verification.

cmake verilator verilog verilog-template

Last synced: 15 Nov 2024

https://github.com/ain1084/audio_level_meter

This is an audio level meter implemented using Verilog HDL.

audio machxo2 verilog visualization

Last synced: 20 Dec 2024

https://github.com/calint/tang-nano-9k--riscv

RISC-V rv32i implementation on Tang Nano 9K

risc-v rv32i tang-nano-9k verilog

Last synced: 10 Jan 2025

https://github.com/dpieve/university

A resource for students learning programming and personal reference.

assembly cpp haskell haskell-exercises java matlab prolog python shell unifei-university verilog

Last synced: 22 Dec 2024

https://github.com/coldnew/nand2tetris

My notes and impement on Nand2Tetris courses

coursearea nand2tetris personal-notes verilator verilog

Last synced: 15 Nov 2024

https://github.com/dyna-bytes/fpga_winter_internship_2020

[Korea University Elementary Particle Physics Lab] Hardware control research using FPGA

fpga rtl verilog vhdl

Last synced: 02 Dec 2024

https://github.com/dyna-bytes/fisr

Specialized FPU for Fast Inverse Square Root Algorithm

fpu verilog

Last synced: 02 Dec 2024

https://github.com/justin-marian/tiny-risc-v

Minimalist RISC-V with a five-stage pipeline. It serves as a platform for understanding processor design principles.

isa-architecture risc-v-architecture verilog

Last synced: 27 Dec 2024

https://github.com/seyed0123/vendor

A vending machine system

verilog

Last synced: 24 Nov 2024

https://github.com/ranitmanik/cs-verilog-assignments

A collection of Verilog code snippets and assignments for computer science coursework.

assignment coding iverilog low-level-programming practice practice-programming verilog

Last synced: 30 Nov 2024

https://github.com/chili-chips-ba/uberclock

Digital systems are clocked. This project is about constructed a high-Q clock by simmering an ordinary quartz in a heavy numerical "secret sauce" that is fully open to the public.

clock-generator crystal dsp fpga risc-v rtl stratum-2 verilog

Last synced: 06 Dec 2024

https://github.com/justin-marian/fsm-vending-machine

FSM vending machine, it dispenses products based on user input and provides change based on the money introduced.

fsm vending-machine-proplem verilog

Last synced: 27 Dec 2024

https://github.com/calint/riscv

experiments implementing a risc-v cpu to gain experience with verilog and minimalistic cpu design

cmod-s7 cpu fpga iverilog risc-v riscv32i verilog vivado

Last synced: 10 Jan 2025

https://github.com/thedhruvrawat/comparch

This repository contains all the laboratory coursework for the course CS F342: Computer Architechture at BITS Pilani, Pilani Campus (Fall '22)

computer-architecture verilog

Last synced: 03 Jan 2025

https://github.com/toruniina/brainfxck-circuit

run brainfxck on FPGA

brainfuck verilog

Last synced: 08 Dec 2024

https://github.com/shiro-raven/verilog-mips

A verilog-based MIPS processor with pipelining

assembly mips mips-architecture verilog

Last synced: 05 Dec 2024

https://github.com/taffarel55/verilog

Documentação dos exemplos que fiz enquanto estudava a linguagem de descrição de hardware Verilog.

verilog verilog-examples verilog-hdl

Last synced: 09 Jan 2025

https://github.com/jjateen/snake-game-verilog

This repository showcases a Verilog-based Snake and Apple Game, developed for the ECL 106: Digital System Design with HDL course. Running on an Altera DE10-Lite FPGA board and displayed on a VGA monitor, players control a snake to collect apples while avoiding obstacles. The snake grows longer with each apple, making the game progressively harder.

altera-fpga de10-lite fpga quartus-prime verilog verilog-project

Last synced: 16 Nov 2024

https://github.com/guntas-13/verilog

Compilation of all the Verilog Assignments in the course ES204 - Digital Systems (Spring 2024) - Prof. Joycee Mekie

verilog verilog-hdl

Last synced: 03 Dec 2024

https://github.com/peplxx/morse-coder

This project was made for optional fpga project during F23 Computer Architecture course. This is Quartus Project for turning fpga board into morse coder.

fpga-board fpga-programming morse-code quartus-prime verilog

Last synced: 20 Dec 2024

https://github.com/strwdr/MaximatorZXSpectrum

ZX Spectrum implementation for maximator board

board fpga hdl max10 maximator nios soc verilog zx zx-spectrum

Last synced: 24 Oct 2024

https://github.com/jminjares4/digital-system-2

Digital System 2 Lab

digital-design verilog

Last synced: 10 Jan 2025

https://github.com/kulp/tappy

tappy is a tiny Verilog driver for PS/2 keyboards, for use in FPGAs

fpga verilog

Last synced: 16 Dec 2024

https://github.com/qasimwani/karnaugh-map-batch-calculator

Calculates Multiple Karnaugh Maps at once using Selenium and custom built parser. The program then converts the Boolean Expressions into Dataflow Verilog (VHDL)

converts dataflow-verilog karnaugh-map karnaugh-map-solver karnaugh-maps selenium verilog web-scraping

Last synced: 27 Dec 2024

https://github.com/arefin994/bitstreamos

BitStreamOS --- A custom-designed MIPS CPU and operating system built from scratch. Features include a custom instruction set, assembler for converting assembly code to binary, CPU simulation with test benches, waveform visualization, and a basic OS implementation.

asm cpu mips-assembly os verilog

Last synced: 01 Jan 2025

https://github.com/youseftareq33/digital_buildcombinationalcircuit_1

Using Verilog HDL on Quartus application build combinational circuit

combinational-circuit verilog

Last synced: 24 Dec 2024

https://github.com/adolbyb/vhdl-fpga-nexys-a7

A collection of code from CDA 4240C: Design of Digital System and Lab

artix-7 fpga hardware-description-language hdl nexys-a7 verilog vhdl xilinx-vivado

Last synced: 19 Nov 2024

Verilog Awesome Lists
awesome-hdl 121 awesome-open-hardware-verification 44 ASIC-Design-Roadmap 83 VHDL-Guide 287 CPLD-Guide 287
Verilog Categories
OpenCL Tools, Libraries and Frameworks 138 C/C++ Tools, Libraries and Frameworks 80 C/C++ Learning Resources 68 MATLAB Tools, Libraries, Frameworks 66 Firmware Tools, Libraries, and Frameworks 56 Assembly Learning Resources 36 MATLAB Learning Resources 34 Meta HDL and Transpilers 32 Projects and IPs 31 Firmware Learning Resources 28 Verilog/SystemVerilog Learning Resources 25 Verilog/SystemVerilog Tools 24 Frameworks: 23 OpenCL Learning Resources 22 HLS 16 Tutorials and Courses 💬[Intro](./Tutorials%20and%20Courses/README.md) 15 Tutorials and Courses 15 PSS : Portable test and Stimulus Standard 14 Awesome Awesome ⭐ 12 HDL simulators and compilers 9