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Verilog

Verilog is a widely-used hardware description language (HDL) that enables designers to model, simulate, and synthesize digital circuits. It provides a text-based format for specifying the structure and behavior of electronic systems, making it easier to design complex hardware components such as microprocessors, memory, and communication devices.

https://github.com/lemongrb/frequencydivider

verilog code for frequency divider circuit implemented with verilog hdl

digital-design fpga frequency-divider hardware-description-language hdl verilog

Last synced: 10 Jan 2025

https://github.com/kar-dim/icsd-digitalsystems

Some Verilog projects, implemented as part of my university coursework (2013-2019, Information and Communications Systems Engineering, University of the Aegean).

verilog

Last synced: 04 Jan 2025

https://github.com/francoriba/alu-uart-basys3

UART modules interface using Verilog for the Basys3 board (Digilent). Computer Architecture 2023. FCEFyN, UNC, Argentina

arquitectura-de-computadores basys3-fpga computerarchitecture fcefyn hardwaredescription uart unc verilog

Last synced: 11 Jan 2025

https://github.com/vincent-g-van/one-time-pad-fpga

64-Bits One-Time Pad on FPGA Board (Nexys 4 DDR Artix-7).

diligent nexys4 one-time-pad otp seven-segment verilog vivado

Last synced: 30 Jan 2025

https://github.com/awrsha/digital-systems

Digital systems lesson with Dr. Vahid Rostami Provided by Qazvin Islamic Azad University

digital-systems-design verilog vhdl-examples

Last synced: 12 Jan 2025

https://github.com/mattjesc/uart-cdc-design

UART Design with CDC, FIFO Buffers, and Dynamic Baud Rate Configuration

cdc fifo fpga uart verilog vivado

Last synced: 18 Jan 2025

https://github.com/rithwikksvr/verilog-snake-game

Last semester we made a Snake Game implemented on Hardware. For this Purpose we used Basys 2 Spartan-3E FPGA, 7x5 LED Matrix and Verilog Programming.

fpga verilog

Last synced: 12 Jan 2025

https://github.com/amir78729/logical-circuits-course-final-project

My Logical Circuits course Final Project - Fall98(2019) - VERILOG

logical-circuits verilog

Last synced: 18 Jan 2025

https://github.com/eshansurendra/uart-fpga

This repository documents a project undertaken as part of the EN2111 Electronic Circuit Design module at the University of Moratuwa, focusing on the implementation of a UART communication link between two FPGA boards.

digital-design embedded-systems fpga quartus-prime systemverilog-hdl testbench uart verilog

Last synced: 18 Jan 2025

https://github.com/ellisgl/driver-yl-3

Verilog code to run the YL-3 8 digit 7 segment display.

seven-segment verilog

Last synced: 19 Jan 2025

https://github.com/mummanajagadeesh/i2c-protocol-verilog

Verilog Implementation of I2C Protocol using Finite State Machine (FSM) design

finite-state-machine fpga fsm i2c i2cprotocol verilog verilog-hdl verilog-project xilinx xilinx-vivado

Last synced: 25 Jan 2025

https://github.com/chayashri2308/parking_management

Parking Management System using Verilog, to identify the occupied and vacant space in a parking lot.

fpga verilog

Last synced: 31 Jan 2025

https://github.com/chayashri2308/vending_machine

A simple Vending Machine design for only one product using Verilog. The user can enter three different currency notes and based on the price of the product, the machine dispenses the product and gives the change.

verilog

Last synced: 31 Jan 2025

https://github.com/m13253/sbmips

Naïve MIPS32-like CPU design with pipeline on a Xilinx FPGA

fpga mips mips32 verilog

Last synced: 01 Feb 2025

https://github.com/sauravmaheshkar/verilog-template

❄️ Template for Verilog Projects using iverilog and gtkwave (nix devShell supported)

hardware-description-language template-project verilog verilog-template vhdl

Last synced: 01 Feb 2025

https://github.com/jn513/estudos_verilog

Exemplos feito em verilog para estudos

fpga fpga-programming hardware verilog verilog-code verilog-hdl

Last synced: 08 Feb 2025

https://github.com/theoplayz2/eda-explorer

Инструмент на Python для разведочного анализа данных (EDA) и визуализации, поддерживающий загрузку данных CSV и JSON, с модульной архитектурой ООП. Практическая работа по теме: "Обнаружение и визуализация данных для понимания их сущности" дисциплины "МДК 13.01: Основы применения методов искусственного интеллекта в программировании".

analysis battery-life cqrs csharp data-analysis eeg-analysis exploratorydataanalysis json-visualization matplotlib messaging profile-report python verilog visualization

Last synced: 28 Jan 2025

https://github.com/shiro-raven/verilog-mips

A verilog-based MIPS processor with pipelining

assembly mips mips-architecture verilog

Last synced: 01 Feb 2025

https://github.com/seojuncha/fromthetransistor-fork

geohot's fromthetransistor project with a little modification.

assembler assembly c compiler fromthetransistor python uart verilog

Last synced: 05 Feb 2025

https://github.com/ranitmanik/cs-verilog-assignments

A collection of Verilog code snippets and assignments for computer science coursework.

assignment coding iverilog low-level-programming practice practice-programming verilog

Last synced: 28 Jan 2025

https://github.com/samiyaalizaidi/fpga

Verilog implementation of the basic structure of an FPGA

digital-system-design fpga verilog vivado

Last synced: 16 Jan 2025

https://github.com/samiyaalizaidi/pipelined-risc-v-processor

A Pipelined RISC-V Processor with forwarding support and hazard detection.

assembly computer-architecture pipelining processor processor-architecture risc-v verilog vivado

Last synced: 16 Jan 2025

https://github.com/skpro-glitch/resume

Find my resume, encapsulating my most prominent projects and experiences relevant for an entry level Hardware Engineering role. - Soham Kapur

algorithms-and-data-structures cadence cadence-virtuoso drone electronics-engineering java java-programming ltspice matlab soham-kapur sohamkapur team-aviators-international uav verilog verilog-hdl verilog-processor vit-chennai vit-university vitc vitchennai

Last synced: 05 Feb 2025

https://github.com/jminjares4/digital-system-2-template

Digital System 2 Template

digital-design verilog

Last synced: 10 Jan 2025

https://github.com/shishir-dey/pcb-dev-fpga-ice40

A 2 layer development board with a Lattice Semiconductor ICE40UP5K-SG48ITR FPGA. Made with KiCad

development-board fpga hardware pcb-design verilog

Last synced: 14 Jan 2025

https://github.com/clementkim/logic-circuit-verilog

아주대학교 논리회로 - Verilog를 이용한 프로젝트 코드

logic-circuit verilog

Last synced: 08 Feb 2025

https://github.com/ilovebacteria/elevator-state-machine

My Digital Logic course project - Elevator state machine

digital-logic moore-machine state-machine verilog

Last synced: 14 Nov 2024

https://github.com/jminjares4/digital-system-2

Digital System 2 Lab

digital-design verilog

Last synced: 10 Jan 2025

https://github.com/princeranjan03/imageencryption_i-chip

This project focuses on creating a hardware-based encryption and decryption system that implements the Data Encryption Standard (DES) algorithm.

cipher cryptography data-encryption data-encryption-standard encoding encryption-decryption fpga image image-processing opencv rtldesign source-coding verilog verilog-hdl verilog-project vivado xilinx xilinx-vivado

Last synced: 31 Jan 2025

https://github.com/assem-elqersh/mips-processor-designs

Comprehensive repository containing Verilog implementations of MIPS processors. Includes both single-cycle and multi-cycle architectures, each in separate directories, with full simulation testbenches and modular design components for educational and development purposes.

computer-architecture educational hardware-designs mips mips-architecture processor-design simulation verilog

Last synced: 27 Jan 2025

https://github.com/lasithaamarasinghe/uart-implementation-in-fpga

This is a group assignment done under semester 4 module EN2111:Electronic Circuit Design, .

fpga quartus-prime uart verilog

Last synced: 10 Jan 2025

https://github.com/1sand0s/ssp-master-and-slave-verilog-module

FSM based SPI/SSP Master and Slave Verilog Module

fifo-buffer rtl verilog verilog-hdl

Last synced: 08 Feb 2025

https://github.com/tanmayv25/microprocessor-system-design

Contains the lab work of Microprocessor System Design. All the FPGA prototyping, Drivers and OS modules.

fpga-soc linux-kernel-module sensor-devices verilog xilinx-vivado

Last synced: 30 Dec 2024

https://github.com/et312/custom_cpu

Custom 16-bit RISC-based CPU with custom control unit, ALU, and memory block designs

fpga verilog

Last synced: 08 Feb 2025

https://github.com/kaleid-liner/fpga-tetris

Tetris based on Nexys4 DDR FPGA Board

fpga tetris verilog

Last synced: 16 Jan 2025

https://github.com/radinshahdaei/ce40223-dsd

Practical assignments and projects for "Digital Systems Design".

verilog

Last synced: 28 Jan 2025

https://github.com/sunzey/cpu_project

recording codes of CPU under mips ISA in lecture of computer organization

buaa buaa-co cpu learning verilog

Last synced: 16 Jan 2025

https://github.com/soham9284/smart-home-automation-system

The Smart Home Automation System is a comprehensive solution that integrates sensors, manual controls, and automated logic to manage lighting, temperature, security, and emergency responses efficiently.

fpga fpga-board verilog xilinx-vivado

Last synced: 02 Feb 2025

https://github.com/calint/znxcr

experimental retro 16 bit cpu written in verilog xilinx vivado intended for fpga Cmod S7 from Digilent

16-bit cmod-s7 cpu fpga verilog

Last synced: 10 Jan 2025

https://github.com/calint/tang-nano-9k--riscv

RISC-V rv32i implementation on Tang Nano 9K

risc-v rv32i tang-nano-9k verilog

Last synced: 10 Jan 2025

https://github.com/taffarel55/verilog

Documentação dos exemplos que fiz enquanto estudava a linguagem de descrição de hardware Verilog.

verilog verilog-examples verilog-hdl

Last synced: 09 Jan 2025

https://github.com/calint/riscv

experiments implementing a risc-v cpu to gain experience with verilog and minimalistic cpu design

cmod-s7 cpu fpga iverilog risc-v riscv32i verilog vivado

Last synced: 10 Jan 2025

https://github.com/sofiavalos/verilog_ethernet_10g_mac

Bloques y bancos de pruebas MAC para Ethernet 10G.

ethernet mac verilog

Last synced: 06 Feb 2025

https://github.com/kaushalmodi/nim-svvpi

Wrapper for SystemVerilog VPI headers sv_vpi_user.h and vpi_user.h

1364-2005 1800-2017 nim pli systemverilog verilog vpi

Last synced: 16 Jan 2025

https://github.com/pawel2000pl/verilogleddriver

Led RGB driver written in verilog, implemented for Mimas A7 Mini FPGA Development Board

fpga led-controller led-driver pwm pwm-driver systemverilog verilog vivado

Last synced: 22 Jan 2025

https://github.com/vlad-ivanov-name/verilog-zeroall

Resets all register to zero in a Verilog design

modelsim verilog

Last synced: 31 Jan 2025

https://github.com/coldnew/nand2tetris

My notes and impement on Nand2Tetris courses

coursearea nand2tetris personal-notes verilator verilog

Last synced: 15 Jan 2025

https://github.com/arefin994/bitstreamos

BitStreamOS --- A custom-designed MIPS CPU and operating system built from scratch. Features include a custom instruction set, assembler for converting assembly code to binary, CPU simulation with test benches, waveform visualization, and a basic OS implementation.

asm cpu mips-assembly os verilog

Last synced: 01 Jan 2025

https://github.com/youseftareq33/digital_buildcombinationalcircuit_1

Using Verilog HDL on Quartus application build combinational circuit

combinational-circuit verilog

Last synced: 24 Dec 2024

https://github.com/cosminpopescu14/fpga

Sisteme FPGA

fpga verilog

Last synced: 25 Dec 2024

https://github.com/rogerfan48/course-soph1-hdl

Materials and coursework for Hardware Design Lab (Sophomore Fall). Contains exercises, assignments, and laboratory work.

verilog vivado

Last synced: 08 Jan 2025

https://github.com/saifalomari99/fpga_projects_saifalomari

This Repository is to showcase Saif Alomari's FPGA projects. Includes 25 high-level FPGA projects in various HDLs.

fpga systemverilog verilog

Last synced: 28 Dec 2024

https://github.com/birdybro/nand2tetris_mister

Nand2Tetris for MiSTer (as a learning experience for me).

hdl mister misterfpga tetris verilog verilog-hdl

Last synced: 01 Feb 2025

https://github.com/davidvarshanidze/cpu

CPU implementation in MIPS Assembly and Verilog

cpu mips-assembly verilog

Last synced: 04 Feb 2025

https://github.com/niw/chisel_test

A simple Chisel test project for myself to learn Chisel and FPGA.

chisel3 fpga orangecrab scala tinyfpga verilog

Last synced: 06 Jan 2025

https://github.com/sea-n/nctu-108b-dcd

108 Spring - Digital Circuit Design

homework nctu verilog

Last synced: 07 Jan 2025

https://github.com/roscibely/arithmetic-logic-unit

A simple arithmetic logic unit (ALU) with System verilog

alu arithmetic verilog vhdl

Last synced: 21 Jan 2025

https://github.com/camilaqpereira/oficina-verilog-siecomp

Neste repositórios estão disponibilizados todos os arquivos utilizados na Oficina Introdução ao Verilog Comportamental ministrado na XXXI SIECOMP (UEFS). Além disso, estão listados múltiplos recursos para estudo da linguagem.

oficina verilog verilog-code verilog-hdl

Last synced: 23 Jan 2025

https://github.com/kitune-san/kfmmc_v2

Multi media card access controller written in HDL

hdl mmc multimediacard sdc sdcard verilog verilog-hdl

Last synced: 21 Jan 2025

https://github.com/kitune-san/kf76489

KF76489 - 76489-like Digital Complex Sound generator written in SystemVerilog

fpga sn76489 systemverilog verilog

Last synced: 21 Jan 2025

https://github.com/azazhassankhan/verilogutilitysuite

VerilogUtilitySuite 🚀 Welcome to our SystemVerilog playground! 🤖 Dive into the world of hardware description language (HDL) with our repository, where RTL designs meet creativity.

circuit component-architecture systemverilog verilog

Last synced: 21 Jan 2025

https://github.com/calint/zen-one

experimental retro 16 bit cpu written in verilog xilinx vivado intended for fpga cmod s7 from digilent

16-bit cmod-s7 cpu fpga iverilog verilog vintage vivado

Last synced: 10 Jan 2025

https://github.com/xigh/tinyfpga-counter

simple 1hz tinyfpga counter

fpga tinyfpga-bx verilog

Last synced: 08 Jan 2025

https://github.com/dibahk/verilog-language

A collection of verilog codes

gates verilog

Last synced: 08 Jan 2025

https://github.com/guntas-13/verilog

Compilation of all the Verilog Assignments in the course ES204 - Digital Systems (Spring 2024) - Prof. Joycee Mekie

verilog verilog-hdl

Last synced: 30 Jan 2025

https://github.com/guntas-13/mips-processor-basys3

Full FPGA Implementation of 32-bit FSM-based Multi-State MIPS Processor

mips-assembly mips-processor processor-architecture verilog

Last synced: 30 Jan 2025

https://github.com/youseftareq33/digital_buildcombinationalcircuit_2

Using Verilog HDL on Quartus application build combinational circuit

combinational-circuit verilog

Last synced: 24 Dec 2024

https://github.com/javiidiazglez/ec

Estructuras de Computadores

verilog

Last synced: 01 Jan 2025

https://github.com/mongshil553/digital-engineering-verilog-assignments

Sophomore 2021 1st Semester Digital Engineering Verilog Assignments

fpga-programming verilog xilinx-vivado

Last synced: 13 Jan 2025

https://github.com/calint/tang-nano-20k--riscv--cache-sdram

RISC-V implementation of rv32i for FPGA board Tang Nano 20K utilizing on-board burst SDRAM and flash

fpga risc-v rv32i systemverilog tang-nano-20k verilog

Last synced: 03 Jan 2025

https://github.com/andrejchoo/fpga_wav_player

A simple project for playing wav files on FPGA or CPLD

fpga spi-flash verilog wav

Last synced: 03 Jan 2025

https://github.com/karagultm/datapath

The project involved extending the processor to support six new instructions: brv, jmxor, nori, blezal, jalpc, and baln. This required modifications to the control logic, the addition of new multiplexers, and the inclusion of status register flags to handle the specific behaviors of these instructions.

mips mips-architecture mips-assembly verilog

Last synced: 24 Dec 2024

https://github.com/3-o-3/cod5

Public Domain (⊄) Computer on FPGA

fpga fpga-soc public-domain ternary ternary-computer verilog

Last synced: 11 Feb 2025

https://github.com/thedhruvrawat/comparch

This repository contains all the laboratory coursework for the course CS F342: Computer Architechture at BITS Pilani, Pilani Campus (Fall '22)

computer-architecture verilog

Last synced: 03 Jan 2025

https://github.com/urish/tt06-spell

A minimal, stack-based programming language created for The Skull CTF

tinytapeout verilog wizardry

Last synced: 11 Jan 2025

https://github.com/panxuc/xucpu

NSCSCC “龙芯杯” 2024 个人赛 LoongArch 赛道参赛作品

fpga loongarch nscscc verilog

Last synced: 01 Feb 2025

https://github.com/mssola/hdl

Playing around with Hardware Description Languages.

hdl systemverilog verilog

Last synced: 27 Jan 2025

https://github.com/woolseyworkshop/article-creating-a-configurable-multifunction-logic-gate-in-verilog

Creating A Configurable Multifunction Logic Gate In Verilog Article Resources

digital-logic verilog

Last synced: 29 Dec 2024

https://github.com/woolseyworkshop/article-getting-started-with-the-tinyfpga-bx

Getting Started With The TinyFPGA BX Article Resources

electronics programming tinyfpga-bx verilog

Last synced: 29 Dec 2024

https://github.com/atoomnetmarc/fpga-playground

Random collection of FPGA related stuff.

apio fpga hdlbits ice40 ice40hx8k icestorm verilog yosys

Last synced: 03 Feb 2025

https://github.com/davidf1000/sistemdigital_vhdl

Final Project for Digital System Lab. Flappy Bird Imitation Game created using VHDL for FPGA DE1.

fpga quartus verilog vhdl

Last synced: 11 Jan 2025

https://github.com/mohamad-shosha/alu-verilog-proteus

This 4-bit ALU design project has been implemented as part of the [Computer Aided Design] in the university , where we applied Verilog for hardware design and Proteus for simulation.

proteus verilog

Last synced: 28 Dec 2024

https://github.com/shpegun60/open_std_fpga

This std libraries on fpga

fpga-std standard-library-fpga verilog

Last synced: 18 Jan 2025

Verilog Awesome Lists
awesome-hdl 121 awesome-open-hardware-verification 44 ASIC-Design-Roadmap 83 VHDL-Guide 287 CPLD-Guide 287
Verilog Categories
OpenCL Tools, Libraries and Frameworks 139 C/C++ Tools, Libraries and Frameworks 80 C/C++ Learning Resources 68 MATLAB Tools, Libraries, Frameworks 66 Firmware Tools, Libraries, and Frameworks 56 Assembly Learning Resources 36 MATLAB Learning Resources 34 Meta HDL and Transpilers 32 Projects and IPs 31 Firmware Learning Resources 28 Verilog/SystemVerilog Learning Resources 25 Verilog/SystemVerilog Tools 24 Frameworks: 23 OpenCL Learning Resources 22 HLS 16 Tutorials and Courses 💬[Intro](./Tutorials%20and%20Courses/README.md) 15 Tutorials and Courses 15 PSS : Portable test and Stimulus Standard 14 Awesome Awesome ⭐ 12 HDL simulators and compilers 9