https://github.com/liu42/pipeline

《计算机组成原理》课程设计，基于 MIPS 系统的流水线 CPU 设计

architecture computer-architecture course-project cpu fpga homework-project mips mips-architecture mips-processor pipeline verilog

Last synced: 23 Nov 2024

https://github.com/kkkaan/metu-ceng-thes

Some of the homeworks I have done at metu ceng.

bash c clingo cpp haskell java prolog python quantum-computing verilog

Last synced: 04 Jan 2025

https://github.com/standardsemiconductor/veldt-blinker-verilog

VELDT blinker example with verilog

veldt verilog

Last synced: 12 Nov 2024

https://github.com/rambodrahmani/dalle_porte_and_or_not_al_sistema_calcolatore

Dalle Porte AND OR NOT Al Sistema Calcolatore. Un viaggio nel mondo delle reti logiche in campagnia del linguaggio Verilog.

altera boolean-algebra boolean-logic logic-gates modelsim verilog

Last synced: 29 Dec 2024

https://github.com/junzhengca/space-enemies

Rip off of space invaders coded in Verilog with VGA output support, intended for DE2-115 FPGA board. Final project for CSCB58.

assignment de2-115 hardware project verilog

Last synced: 13 Dec 2024

https://github.com/weisrc/fpgaudio

MIDI file to Verilog Code Generation - FPGAudio!

midi verilog

Last synced: 23 Dec 2024

https://github.com/weisrc/nesv

NESystem Verilog

basys3 emscripten emulator fpga nes systemverilog verilator verilog vivado webassembly

Last synced: 23 Dec 2024

https://github.com/byte-me404/tt-ps2-morse-encoder

Custom ASIC design which decodes a PS/2 keyboard, furthermore it encodes and outputs the data as morse code

asic morse-code ps2-keyboard tinytapeout verilog

Last synced: 05 Jan 2025

https://github.com/abdallahabusedo/cmp305-introduction-verilog

introduction to Verilog in Integrated Circuit Design And VLSI technology

verilog verilog-code verilog-hdl verilog-project

Last synced: 13 Dec 2024

https://github.com/tmahlburg/mriscv

simple, modular rv32i implementation (WIP)

risc-v riscv riscv32 rv32i verilog verilog-hdl

Last synced: 16 Nov 2024

https://github.com/jgroman/fpga-tangprimer25k-experiments

Learning digital design with Tang Primer 25K

fpga verilog

Last synced: 19 Nov 2024

https://github.com/drom/vpreproc

Verilog preprocessor bindings for Node.js

napi nodejs preprocessor verilog

Last synced: 18 Dec 2024

https://github.com/pavlostzitzos/hdls-intro

SystemVerilog , Verilog , Verilog-A , Verilog-AMS tutorial

verilog verilog-hdl verilog-testbenches vhdl

Last synced: 24 Dec 2024

https://github.com/mgriebling/lola

A digital design language by Nicklaus Wirth, similar to VHDL and Verilog, but much simpler and easier to master.

circuit-compiler digital-circuit-design lola simulator swift verilog vhdl wirth

Last synced: 29 Dec 2024

https://github.com/xilover/iot-and-edge-computing

Hands-on learning experience in IoT, edge computing, and embedded systems using a variety of platforms such as microcontrollers (nRF, STM32, ESP32), FPGAs (Xilinx), and SoCs (Raspberry Pi, Zynq).

aws-iot azure-iot ble circuit-design edge-computing esp32 fpga iot mqtt nrf pynq-z2 raspberry-pi rtos stm32 system-on-chip verilog vhdl vivado xilinx xilinx-zynq

Last synced: 18 Dec 2024

https://github.com/chenqianhe/learnprofessionalbasiccoursesincomputerscience

Learn Professional Basic Courses in Computer Science计算机专业基础课程学习

assembly computer-network computer-science computer-system-structure cpp operating-system principle-of-computer-composition professional-basic-courses verilog

Last synced: 18 Nov 2024

https://github.com/zazi2002/computer-architectur-lab

Computer Architecture Lab projects with various fundamental concepts, including multi-cycle MIPS processors and PIC32 microcontroller programming.

counter mips multicycle-processor pic32 verilog

Last synced: 28 Dec 2024

https://github.com/ellisgl/driver-yl-3

Verilog code to run the YL-3 8 digit 7 segment display.

seven-segment verilog

Last synced: 18 Nov 2024

https://github.com/ellisgl/addressable-debouncer-verilog

Addressable 8 SPDT debouncer in Verilog

cpld debounce debounce-button debouncing fpga verilog

Last synced: 18 Nov 2024

https://github.com/acmachado14/circuitoscombinacionais

Circuitos Combinacionais em Verilog | Trabalho pratico pra disciplina de Introdução aos Sistemas Lógicos - UFV

verilog

Last synced: 20 Nov 2024

https://github.com/alyssonmach/sistema-seguranca-residencial

Projeto final da disciplina Laboratório de Circuitos Lógicos - Sistema de Segurança Residencial.

logic-circuit logic-gates logisim project ufcg verilog

Last synced: 24 Dec 2024

https://github.com/harshalmittal4/24-bit-risc-processor

Computer Architecture-MIPS Processor simulation in verilog with self developed ISA

isa risc-processor verilog

Last synced: 19 Nov 2024

https://github.com/valaphee/redsynth

Generate redstone circuits out of Verilog.

bukkit-plugin fpga minecraft redstone synthesis verilog

Last synced: 07 Jan 2025

https://github.com/blagojeblagojevic/vga_verilog

Implementation of a vga interface on a Basys 3 FPGA

fpga verilog

Last synced: 21 Dec 2024

https://github.com/rauhul/ece385

Digital Systems Laboratory UIUC FA 2016

altera fpga quartus-prime systemverilog verilog

Last synced: 02 Dec 2024

https://github.com/xtrinch/icestick-fpga-example

Example project for Lattice icestick fpga

fpga icestorm-toolchain verilog

Last synced: 21 Dec 2024

https://github.com/brlin-tw/clean-filter-for-verilog

Clean your Verilog design code!

bash clean-filter filter git git-attributes istyle vdent verilog

Last synced: 21 Nov 2024

https://github.com/skpro-glitch/riscv-processor-asic

This is a basic RISC-V based processor under development. It follows the 32-bit Integer ISA.

asic asic-design asic-verification fpga hardware-designs open-source openlane openlane-flow processor-architecture processor-design risc-v riscv32 verilog verilog-hdl vlsi vlsi-design

Last synced: 20 Dec 2024

https://github.com/jasonbrave/microsoc

RISC-V SoC

microcontroller risc-v riscv soc system-on-chip systemverilog uart verilog

Last synced: 20 Dec 2024

https://github.com/calint/zen-x

experimental retro 16 bit cpu written in verilog xilinx vivado intended for fpga Cmod S7 from Digilent

16-bit cmod-s7 cpu fpga verilog vintage vivado xilinx

Last synced: 10 Jan 2025

https://github.com/vgalovic/hdl_examples

A collection of VHDL and Verilog examples organized by language and practice section, with setup.tcl files for easy Vivado setup. These examples reflect my FPGA development practice and learning.

tcl verilog vhdl vivado

Last synced: 03 Jan 2025

https://github.com/eshansurendra/uart-fpga

This repository documents a project undertaken as part of the EN2111 Electronic Circuit Design module at the University of Moratuwa, focusing on the implementation of a UART communication link between two FPGA boards.

digital-design embedded-systems fpga quartus-prime systemverilog-hdl testbench uart verilog

Last synced: 17 Nov 2024

https://github.com/jamesits/verilog-basic-blocks

数电作业

verilog verilog-components xilinx-ise

Last synced: 05 Dec 2024

https://github.com/sameer/de2-115-template

HDLMake template for terasIC DE2-115

de2-115 hdlmake template verilog vhdl

Last synced: 18 Dec 2024

https://github.com/jn513/baby-risco-5

Multi-cycle RISC-V processor with RV32E implementation

riscv riscv32 riscv32e verilog verilog-hdl

Last synced: 15 Dec 2024

https://github.com/m13253/sbmips

Naïve MIPS32-like CPU design with pipeline on a Xilinx FPGA

fpga mips mips32 verilog

Last synced: 05 Dec 2024

https://github.com/zhb2000/computerorganizationexperiment

计算机组成与设计课程实验

computer-organization verilog

Last synced: 25 Dec 2024

https://github.com/muhammadtalhasami/rtl_practice

This repository contain basic verilog codes which include the implementation of DLD (digital logic desgin ) circuits.

100daysofrtl hardware-coding muhammadtalhasami-github- rtl testbench verilog verilog-practice vhdl

Last synced: 25 Dec 2024

https://github.com/jn513/estudos_verilog

Exemplos feito em verilog para estudos

fpga fpga-programming hardware verilog verilog-code verilog-hdl

Last synced: 15 Dec 2024

https://github.com/ain1084/dual_clock_buffer

Dual clock buffer for modules connected by valid-ready protocol

protocol-buffers verilog

Last synced: 20 Dec 2024

https://github.com/dvvcz/cpe-133

icarus-verilog iverilog systemverilog verilog vivado

Last synced: 05 Jan 2025

https://github.com/the-pinbo/risc-spm

This project involves the development and enhancement of a RISC Stored-Program Machine (RISC SPM), based on the architecture detailed in "Advanced Digital Design with the Verilog HDL" by Michael D. Ciletti.

computer-architecture riscv verilog

Last synced: 25 Dec 2024

https://github.com/marceldobehere/goofy-cpu-verilog

cpu cpu-simulator goofy goofy-cpu sim verilog

Last synced: 04 Jan 2025

https://github.com/ain1084/serial_audio_encoder

Serial audio encoder

encoder i2s-audio verilog

Last synced: 20 Dec 2024

https://github.com/kar-dim/icsd-digitalsystems

Some Verilog projects, implemented as part of my university coursework (2013-2019, Information and Communications Systems Engineering, University of the Aegean).

verilog

Last synced: 04 Jan 2025

https://github.com/rishabh-agarwal/cisc530-computersystemarchitecture

This repository contain HW and assignment for ComputerSystemArchitecture class at Harrisburg University

assignment cisc530 harrisburg homework kapila university verilog

Last synced: 28 Dec 2024

https://github.com/ghazaleze/microblaze-equation-solver

for solving cubic equation

c fpga verilog

Last synced: 05 Jan 2025

https://github.com/gatsbyz/processor-design-verilog

college stuff

assembly hardware verilog

Last synced: 05 Dec 2024

https://github.com/brosnanyuen/tt07-neuromorphic-asic-with-96-neurons

Neuromorphic ASIC with 96 neurons on Tiny Tapeout 7

asic computational-neuroscience deep-learning fpga machine-learning neural-network neuromorphic neuromorphic-computing pcb snn spiking-neural-networks tinytapeout verilog

Last synced: 13 Nov 2024

https://github.com/delhatch/flipdot_video

Video streaming from a camera to a 58x24 pixel flipdot display. See the two flipdot_display*.mp4 videos. All processing in Verilog RTL (no softcore uP).

altera de2-115 flipdot flipdots fpga verilog

Last synced: 13 Nov 2024

https://github.com/sofiavalos/verilog_ethernet_10g_pcs

Bloques y bancos de pruebas PCS para Ethernet 10G.

ethernet pcs verilog

Last synced: 05 Jan 2025

https://github.com/antonioberna/computer-architecture-engineering

Computer Architecture Engineering (Assembly and C)

assembly c computer-architecture digital verilog vhdl

Last synced: 13 Nov 2024

https://github.com/manighazaee/cpu

CPU architecture implemented in Verilog and its assembler in Rust.

architecture assembler cpu rust verilog

Last synced: 03 Dec 2024

https://github.com/tmahlburg/picosoc-basys3

Wrapper module for the PicoSoC to support the Digilent Basys 3

artix artix-7 basys3 digilent picorv32 picosoc risc-v verilog vivado xilinx

Last synced: 16 Nov 2024

https://github.com/mat1g3r/csc258_final_project

CSC258 final project

verilog

Last synced: 22 Nov 2024

https://github.com/quentinwach/computer-engineering

📝 Notes on computer engineering. From application to custom computer design.

book computer-architecture course cpu cpu-architecture documentation gtkwave hack hack-computer icarus icarus-verilog iverilog logisim nand2tetris nand2tetris-assignments nand2tetris-projects nand2tetris-solutions recources verilog

Last synced: 13 Nov 2024

https://github.com/vincent-g-van/one-time-pad-fpga

64-Bits One-Time Pad on FPGA Board (Nexys 4 DDR Artix-7).

diligent nexys4 one-time-pad otp seven-segment verilog vivado

Last synced: 03 Dec 2024

https://github.com/chaseruskin/verb

An approachable testing framework for digital hardware

framework python simulation system-verilog testing verification verilog vhdl

Last synced: 14 Nov 2024

https://github.com/cmpark0126/mips_32bits

Implements 32bits MIPS with verilog. (18.11.25 ~ 18.12.)

fpga mips32cpu verilog

Last synced: 23 Dec 2024

https://github.com/vivekadi/fpga_verilog_interfacing

Interfacing peripherals to FPGA

fpga interfacing keypad4x4 labs motor-controller singal-generator spartan6 verilog xilinx

Last synced: 14 Nov 2024

https://github.com/rithwikksvr/verilog-snake-game

Last semester we made a Snake Game implemented on Hardware. For this Purpose we used Basys 2 Spartan-3E FPGA, 7x5 LED Matrix and Verilog Programming.

fpga verilog

Last synced: 13 Nov 2024

https://github.com/andrejchoo/cpldctrum

ZX Spectrum clone on CPLD

cpld divmmc verilog zx-spectrum

Last synced: 11 Dec 2024

https://github.com/elifgokpinar/microprocessor-design

Quartus Project

microprocessor quartus verilog

Last synced: 13 Nov 2024

https://github.com/ewdlop/verilog-notes

HDLBit-Pratice. https://hdlbits.01xz.net/wiki/Main_Page

combinational-logic finte-state-machine flip-flops sequential-logic verilog

Last synced: 27 Dec 2024

https://github.com/calint/zen-one

experimental retro 16 bit cpu written in verilog xilinx vivado intended for fpga cmod s7 from digilent

16-bit cmod-s7 cpu fpga iverilog verilog vintage vivado

Last synced: 10 Jan 2025

https://github.com/shiro-raven/verilog-mips

A verilog-based MIPS processor with pipelining

assembly mips mips-architecture verilog

Last synced: 05 Dec 2024

https://github.com/justin-marian/fsm-vending-machine

FSM vending machine, it dispenses products based on user input and provides change based on the money introduced.

fsm vending-machine-proplem verilog

Last synced: 27 Dec 2024

https://github.com/justin-marian/tiny-risc-v

Minimalist RISC-V with a five-stage pipeline. It serves as a platform for understanding processor design principles.

isa-architecture risc-v-architecture verilog

Last synced: 27 Dec 2024

https://github.com/harikrishnan669/verilog

KTU S4 DIGITAL LAB PROGRAMS (VERILOG)

cse ktu-s4-cse verilog

Last synced: 28 Nov 2024

https://github.com/mssola/hdl

Playing around with Hardware Description Languages.

hdl systemverilog verilog

Last synced: 29 Nov 2024

https://github.com/kaushalmodi/nim-svvpi

Wrapper for SystemVerilog VPI headers sv_vpi_user.h and vpi_user.h

1364-2005 1800-2017 nim pli systemverilog verilog vpi

Last synced: 15 Nov 2024

https://github.com/yasnakateb/aes

🔐 Hardware Implementation Of AES Algorithm in Verilog HDL

aes aes-128 aes-encryption encryption encryption-algorithm icarus-verilog iverilog verilog verilog-hdl

Last synced: 19 Nov 2024

https://github.com/yasnakateb/blinky

💡A Quartus II project testing the functionality of the Altera Cyclone IV EP4CE6E22C8N board

altera-fpga fpga verilog verilog-hdl

Last synced: 19 Nov 2024

https://github.com/yasnakateb/uartcommunication

☎️ UART Communication Implementation in Verilog HDL

icarus-verilog iverilog serial-communication uart uart-interface uart-protocol uart-verilog verilog

Last synced: 19 Nov 2024

https://github.com/yasnakateb/threshold

🖼✏️ My first baby steps into the world of image processing

grayscale image-processing threshold verilog verilog-hdl xilinx-ise

Last synced: 19 Nov 2024

https://github.com/yasnakateb/sdramcontroller

🛠 A SDRAM controller in Verilog HDL

icarus-verilog iverilog memory-controller sdram sdram-controller verilog verilog-hdl

Last synced: 19 Nov 2024

https://github.com/qasimwani/karnaugh-map-batch-calculator

Calculates Multiple Karnaugh Maps at once using Selenium and custom built parser. The program then converts the Boolean Expressions into Dataflow Verilog (VHDL)

converts dataflow-verilog karnaugh-map karnaugh-map-solver karnaugh-maps selenium verilog web-scraping

Last synced: 27 Dec 2024

https://github.com/strwdr/MaximatorZXSpectrum

ZX Spectrum implementation for maximator board

board fpga hdl max10 maximator nios soc verilog zx zx-spectrum

Last synced: 24 Oct 2024

https://github.com/peplxx/morse-coder

This project was made for optional fpga project during F23 Computer Architecture course. This is Quartus Project for turning fpga board into morse coder.

fpga-board fpga-programming morse-code quartus-prime verilog

Last synced: 20 Dec 2024

https://github.com/kassane/fpga_course

Testing conducted during verilog studies

fpga verilog

Last synced: 13 Nov 2024

https://github.com/mosure/ece552-project-fall-2018

ece552 uw-madison verilog

Last synced: 29 Nov 2024

https://github.com/aledpl5/rock-paper-scissors-circuit

Uni project about the game rock-paper-scissors

blif circuit datapath datapath-design finate-state-machine sis systemverilog verilog

Last synced: 05 Jan 2025

https://github.com/idorobots/upduino-blinky

Two simple Upduino projects that blink an RGB LED in various ways.

blinky fpga ice40 ice40up5k led upduino upduino-board verilog

Last synced: 20 Dec 2024

https://github.com/roscibely/arithmetic-logic-unit

A simple arithmetic logic unit (ALU) with System verilog

alu arithmetic verilog vhdl

Last synced: 21 Nov 2024

https://github.com/rpigor/tpsim

TPSim (Timing and Power Simulator) is a gate-level circuit simulator with timing and power estimation capabilities

eda power-analysis simulator timing-analysis verilog

Last synced: 06 Jan 2025

https://github.com/mohamad-shosha/alu-verilog-proteus

This 4-bit ALU design project has been implemented as part of the [Computer Aided Design] in the university , where we applied Verilog for hardware design and Proteus for simulation.

proteus verilog

Last synced: 28 Dec 2024

https://github.com/javiidiazglez/ec

Estructuras de Computadores

verilog

Last synced: 01 Jan 2025

https://github.com/niw/chisel_test

A simple Chisel test project for myself to learn Chisel and FPGA.

chisel3 fpga orangecrab scala tinyfpga verilog

Last synced: 06 Jan 2025

https://github.com/saifalomari99/fpga_projects_saifalomari

This Repository is to showcase Saif Alomari's FPGA projects. Includes 25 high-level FPGA projects in various HDLs.

fpga systemverilog verilog

Last synced: 28 Dec 2024

https://github.com/samiyaalizaidi/pipelined-risc-v-processor

A Pipelined RISC-V Processor with forwarding support and hazard detection.

assembly computer-architecture pipelining processor processor-architecture risc-v verilog vivado

Last synced: 16 Nov 2024

https://github.com/sofiavalos/verilog_ethernet_10g_mac

Bloques y bancos de pruebas MAC para Ethernet 10G.

ethernet mac verilog

Last synced: 12 Dec 2024

https://github.com/orcalinux/computer-organization-and-architecture

Verilog code examples and materials for Computer Organization.

8086-microprocessor computer-architecture computer-organization modelsim pic programmable-interrupt-controller qu synthesis-project verilog

Last synced: 20 Dec 2024

https://github.com/chili-chips-ba/uberclock

Digital systems are clocked. This project is about constructed a high-Q clock by simmering an ordinary quartz in a heavy numerical "secret sauce" that is fully open to the public.

clock-generator crystal dsp fpga risc-v rtl stratum-2 verilog

Last synced: 06 Dec 2024

https://github.com/akafael/verilog-sandbox

selflearning tutorial-exercises verilog

Last synced: 29 Nov 2024

https://github.com/ain1084/audio_level_meter

This is an audio level meter implemented using Verilog HDL.

audio machxo2 verilog visualization

Last synced: 20 Dec 2024

https://github.com/ain1084/machxo2_serial_to_spdif_transmitter

Serial (LPCM) to S/PDIF transmitter. Using MachXO2 (1200HC QFN32).

audio machxo2 spdif verilog

Last synced: 20 Dec 2024

https://github.com/dev-ritik/calculator

Xilinx college project

calculator college-project gui java-applet verilog xilinx

Last synced: 03 Dec 2024

https://github.com/prinuvinod/digital-lab

These are some Verilog Programs

digital verilog

Last synced: 06 Jan 2025

https://github.com/j-m-li/3o3

Ternary CPU for EPROM and FLASH memories

eprom public-domain verilog

Last synced: 06 Dec 2024

https://github.com/jackson-nestelroad/verilog-mips-processor

Single-cycle 32-bit MIPS processor implemented in SystemVerilog.

cpu mips processor verilog

Last synced: 01 Dec 2024