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Verilog

Verilog is a widely-used hardware description language (HDL) that enables designers to model, simulate, and synthesize digital circuits. It provides a text-based format for specifying the structure and behavior of electronic systems, making it easier to design complex hardware components such as microprocessors, memory, and communication devices.

https://github.com/lsx-s-software/tiny-riscv-cpu

An implementation of RV32I ISA, including a single-cycle version and a pipelined version.

cpu pipeline risc-v verilog

Last synced: 22 Jan 2025

https://github.com/cpehle/cascade

Cycle based C++ hardware simulation infrastructure

hardware simulation verilog

Last synced: 08 Feb 2025

https://github.com/hywooo/docker-bsv-wsl2

🐋Docker for Bluespec SystemVerilog (BSV) on WSL2, compatible with WangXuan95/BSV_Tutorial_cn. 适用于BSV中文教程的Docker BSV （WSL2）环境。

bluespec-systemverilog bsv docker dockerfile packages systemverilog verilog vivado

Last synced: 29 Oct 2024

https://github.com/grachale/microarchitecture_risc-v_isa

Design of a Processor Microarchitecture Supporting a Chosen Subset of RISC-V ISA Instructions.

assembly isa microarchitecture risc-v verilog

Last synced: 13 Jan 2025

https://github.com/alyssonmach/logic-circuits

Simulations made in the UFCG logic circuit laboratory.

laboratory logic-circuit logisim quartus ufcg verilog

Last synced: 24 Dec 2024

https://github.com/meetps/ee-214

VHDL and Verilog Codes for Digital Lab.

digital-logic fpga verilog vhdl

Last synced: 04 Jan 2025

https://github.com/sedhossein/verilog-bcd-counter-jk-flip-flop

this source is Commercial bcd counter that built with Jk flip-flop in verilog

bcd counter flip-flop logic verilog

Last synced: 17 Jan 2025

https://github.com/kareimgazer/pci_target_device

Verilog simulation for a Target Device on a PCI bus with read and write transactions.

pci pci-devices verilog xilin xilinx-vivado

Last synced: 03 Feb 2025

https://github.com/yaxsomo/iris_cubesat

This Repository is dedicated to FPGA development of the IRIS CubeSat

aerospace cubesat fpga free-space-optical-communiucation satellite verilog vhdl vivado xilinx

Last synced: 11 Jan 2025

https://github.com/eomielan/16-bit-risc-machine

16-bit CPU architecture implementation and verification using SystemVerilog

cpu-architecture systemverilog verilog

Last synced: 30 Dec 2024

https://github.com/andrejchoo/avr_like_core_on_verilog

Soft core with support for the AVR8 instructions on verilog

avr soft-core verilog

Last synced: 05 Feb 2025

https://github.com/phillbush/tbgen

Testbench generator in AWK for Verilog modules

awk testbench testbench-generator testbench-generator-verilog verilog

Last synced: 22 Jan 2025

https://github.com/amirreza81/digital-systems-design

Digital Systems Design - Spring 2023 - Sharif University of Technology

assembly digital-system-design verilog

Last synced: 05 Jan 2025

https://github.com/ain1084/audio_echo_effect

Simple echo effect implementation with digital audio processing.

audio-processing i2s-audio lattice-fpga verilog

Last synced: 13 Feb 2025

https://github.com/andrejchoo/uart_spiflash_programmer_on_fpga

UART programmer SPI FLASH 25-series on FPGA or CPLD

fpga programmer spi-flash verilog

Last synced: 05 Feb 2025

https://github.com/hedhyw/simple-4bit-cpu

Vivado project with example of simple 4bit CPU

cpu mips verilog vivado xilinx

Last synced: 31 Dec 2024

https://github.com/kitune-san/kfpcjr

[WIP] PoC

fpga pcjr verilog

Last synced: 21 Jan 2025

https://github.com/yugr/gatecheck

Yet another Verilog static analyzer

clock-g gating static-analysis static-analyzer verilog

Last synced: 27 Dec 2024

https://github.com/daulpavid/verilog_template

Boilerplate project template for verilog that includes directories for simulation, documentation, and formal verification.

cmake verilator verilog verilog-template

Last synced: 15 Jan 2025

https://github.com/pseudoincorrect/fpga_mcu_wifi

Link between a PC and a FPGA through wifi

c fpga socket verilog wifi

Last synced: 09 Feb 2025

https://github.com/jgroman/fpga-tangprimer25k-experiments

Learning digital design with Tang Primer 25K

fpga verilog

Last synced: 20 Jan 2025

https://github.com/byte-me404/jku-tt06-ps2-morse-encoder

Custom ASIC design which decodes a PS/2 keyboard, furthermore it encodes and outputs the data as morse code

asic ps2-keyboard tinytapeout verilog

Last synced: 05 Jan 2025

https://github.com/urish/tt05-silife-8x8

Game of Life in Silicon (8x8)

game-of-life tiny-tapeout verilog

Last synced: 11 Jan 2025

https://github.com/tomarus/midirouter

CMOD-A7 FPGA MIDI Merger/Router/Switch.

fpga midi verilog

Last synced: 08 Feb 2025

https://github.com/sofiavalos/verilog_ethernet_10g_pcs

Bloques y bancos de pruebas PCS para Ethernet 10G.

ethernet pcs verilog

Last synced: 05 Jan 2025

https://github.com/engineersbox/cbox16-processor

Implementation of QuAC v1.0 ISA microarchitecture called CBox16

arm armv7 cbox16 cpu isa microarchitecture mips mipsiv quac verilog vhdl

Last synced: 27 Jan 2025

https://github.com/standardsemiconductor/veldt-blinker-verilog

VELDT blinker example with verilog

veldt verilog

Last synced: 11 Jan 2025

https://github.com/weisrc/fpgaudio

MIDI file to Verilog Code Generation - FPGAudio!

midi verilog

Last synced: 23 Dec 2024

https://github.com/pavlostzitzos/hdls-intro

SystemVerilog , Verilog , Verilog-A , Verilog-AMS tutorial

verilog verilog-hdl verilog-testbenches vhdl

Last synced: 24 Dec 2024

https://github.com/xilover/iot-and-edge-computing

Hands-on learning experience in IoT, edge computing, and embedded systems using a variety of platforms such as microcontrollers (nRF, STM32, ESP32), FPGAs (Xilinx), and SoCs (Raspberry Pi, Zynq).

aws-iot azure-iot ble circuit-design edge-computing esp32 fpga iot mqtt nrf pynq-z2 raspberry-pi rtos stm32 system-on-chip verilog vhdl vivado xilinx xilinx-zynq

Last synced: 18 Dec 2024

https://github.com/alyssonmach/sistema-seguranca-residencial

Projeto final da disciplina Laboratório de Circuitos Lógicos - Sistema de Segurança Residencial.

logic-circuit logic-gates logisim project ufcg verilog

Last synced: 24 Dec 2024

https://github.com/calint/zen-x

experimental retro 16 bit cpu written in verilog xilinx vivado intended for fpga Cmod S7 from Digilent

16-bit cmod-s7 cpu fpga verilog vintage vivado xilinx

Last synced: 10 Jan 2025

https://github.com/jn513/baby-risco-5

Multi-cycle RISC-V processor with RV32E implementation

riscv riscv32 riscv32e verilog verilog-hdl

Last synced: 08 Feb 2025

https://github.com/sameer/de2-115-template

HDLMake template for terasIC DE2-115

de2-115 hdlmake template verilog vhdl

Last synced: 11 Feb 2025

https://github.com/tmahlburg/mriscv

simple, modular rv32i implementation (WIP)

risc-v riscv riscv32 rv32i verilog verilog-hdl

Last synced: 17 Jan 2025

https://github.com/tmahlburg/picosoc-basys3

Wrapper module for the PicoSoC to support the Digilent Basys 3

artix artix-7 basys3 digilent picorv32 picosoc risc-v verilog vivado xilinx

Last synced: 17 Jan 2025

https://github.com/euripedesrocha/tbpp

A simple test library for verilator

cpp fusesoc verilator verilog

Last synced: 28 Jan 2025

https://github.com/rishabh-agarwal/cisc530-computersystemarchitecture

This repository contain HW and assignment for ComputerSystemArchitecture class at Harrisburg University

assignment cisc530 harrisburg homework kapila university verilog

Last synced: 28 Dec 2024

https://github.com/sgq995/rc4-de0-nano-soc

It's a cryptoprocessor that implements de RC4 algorithm

de0-nano-soc fpga fpga-soc rc4 verilog

Last synced: 07 Jan 2025

https://github.com/peplxx/morse-coder

This project was made for optional fpga project during F23 Computer Architecture course. This is Quartus Project for turning fpga board into morse coder.

fpga-board fpga-programming morse-code quartus-prime verilog

Last synced: 13 Feb 2025

https://github.com/muhammadtalhasami/rtl_practice

This repository contain basic verilog codes which include the implementation of DLD (digital logic desgin ) circuits.

100daysofrtl hardware-coding muhammadtalhasami-github- rtl testbench verilog verilog-practice vhdl

Last synced: 25 Dec 2024

https://github.com/the-pinbo/risc-spm

This project involves the development and enhancement of a RISC Stored-Program Machine (RISC SPM), based on the architecture detailed in "Advanced Digital Design with the Verilog HDL" by Michael D. Ciletti.

computer-architecture riscv verilog

Last synced: 25 Dec 2024

https://github.com/abtinz/logic-circuits-final-project

Aut Logic Circuits Finall Project Fall 1400

verilog

Last synced: 12 Jan 2025

https://github.com/drom/vpreproc

Verilog preprocessor bindings for Node.js

napi nodejs preprocessor verilog

Last synced: 10 Feb 2025

https://github.com/dyna-bytes/fisr

Specialized FPU for Fast Inverse Square Root Algorithm

floating-point fpu hardware-acceleration verilog

Last synced: 30 Jan 2025

https://github.com/hiyouga/digic-experiment

BUAA CST Autumn 2018 Digital Circuit Experiment

digital-circuit verilog

Last synced: 14 Feb 2025

https://github.com/adolbyb/vhdl-fpga-nexys-a7

A collection of code from CDA 4240C: Design of Digital System and Lab

artix-7 fpga hardware-description-language hdl nexys-a7 verilog vhdl xilinx-vivado

Last synced: 20 Jan 2025

https://github.com/lemongrb/frequencydivider

verilog code for frequency divider circuit implemented with verilog hdl

digital-design fpga frequency-divider hardware-description-language hdl verilog

Last synced: 10 Jan 2025

https://github.com/mgriebling/lola

A digital design language by Nicklaus Wirth, similar to VHDL and Verilog, but much simpler and easier to master.

circuit-compiler digital-circuit-design lola simulator swift verilog vhdl wirth

Last synced: 29 Dec 2024

https://github.com/rauhul/ece385

Digital Systems Laboratory UIUC FA 2016

altera fpga quartus-prime systemverilog verilog

Last synced: 29 Jan 2025

https://github.com/marialmeida1/study-ac

Atividades de Arquitetura de Computadores 1

arquitetura-de-computadores java python verilog

Last synced: 05 Jan 2025

https://github.com/zhb2000/computerorganizationexperiment

计算机组成与设计课程实验

computer-organization verilog

Last synced: 25 Dec 2024

https://github.com/kar-dim/icsd-digitalsystems

Some Verilog projects, implemented as part of my university coursework (2013-2019, Information and Communications Systems Engineering, University of the Aegean).

verilog

Last synced: 04 Jan 2025

https://github.com/francoriba/alu-uart-basys3

UART modules interface using Verilog for the Basys3 board (Digilent). Computer Architecture 2023. FCEFyN, UNC, Argentina

arquitectura-de-computadores basys3-fpga computerarchitecture fcefyn hardwaredescription uart unc verilog

Last synced: 11 Jan 2025

https://github.com/tm90/verilogmodules

generic Verilog modules for reuse...

generic-verilog-modules systemverilog verilog

Last synced: 13 Jan 2025

https://github.com/liu42/pipeline

《计算机组成原理》课程设计，基于 MIPS 系统的流水线 CPU 设计

architecture computer-architecture course-project cpu fpga homework-project mips mips-architecture mips-processor pipeline verilog

Last synced: 23 Nov 2024

https://github.com/vincent-g-van/one-time-pad-fpga

64-Bits One-Time Pad on FPGA Board (Nexys 4 DDR Artix-7).

diligent nexys4 one-time-pad otp seven-segment verilog vivado

Last synced: 30 Jan 2025

https://github.com/hugech38/mips

🐢 用 Verilog 实现的单周期 MIPS 指令集的 CPU，并用它来计算斐波那契数。

cpu mips mips-architecture mips-instructions mips-processor verilog vhdl

Last synced: 21 Jan 2025

https://github.com/byte-me404/tt-ps2-morse-encoder

Custom ASIC design which decodes a PS/2 keyboard, furthermore it encodes and outputs the data as morse code

asic morse-code ps2-keyboard tinytapeout verilog

Last synced: 05 Jan 2025

https://github.com/awrsha/digital-systems

Digital systems lesson with Dr. Vahid Rostami Provided by Qazvin Islamic Azad University

digital-systems-design verilog vhdl-examples

Last synced: 12 Jan 2025

https://github.com/acmachado14/circuitoscombinacionais

Circuitos Combinacionais em Verilog | Trabalho pratico pra disciplina de Introdução aos Sistemas Lógicos - UFV

verilog

Last synced: 21 Jan 2025

https://github.com/mattjesc/uart-cdc-design

UART Design with CDC, FIFO Buffers, and Dynamic Baud Rate Configuration

cdc fifo fpga uart verilog vivado

Last synced: 18 Jan 2025

https://github.com/rithwikksvr/verilog-snake-game

Last semester we made a Snake Game implemented on Hardware. For this Purpose we used Basys 2 Spartan-3E FPGA, 7x5 LED Matrix and Verilog Programming.

fpga verilog

Last synced: 12 Jan 2025

https://github.com/amir78729/logical-circuits-course-final-project

My Logical Circuits course Final Project - Fall98(2019) - VERILOG

logical-circuits verilog

Last synced: 18 Jan 2025

https://github.com/eshansurendra/uart-fpga

This repository documents a project undertaken as part of the EN2111 Electronic Circuit Design module at the University of Moratuwa, focusing on the implementation of a UART communication link between two FPGA boards.

digital-design embedded-systems fpga quartus-prime systemverilog-hdl testbench uart verilog

Last synced: 18 Jan 2025

https://github.com/ethanuppal/hardfloat-spade

Spade wrappers for the Berkley Hardfloat floating-point library

berkeley floating-point hardware verilog

Last synced: 07 Feb 2025

https://github.com/xtrinch/icestick-fpga-example

Example project for Lattice icestick fpga

fpga icestorm-toolchain verilog

Last synced: 14 Feb 2025

https://github.com/vitalyankh/open-fpga-tutorial

Open FPGA Tutorial

chisel fpga verilog

Last synced: 11 Jan 2025

https://github.com/ellisgl/driver-yl-3

Verilog code to run the YL-3 8 digit 7 segment display.

seven-segment verilog

Last synced: 19 Jan 2025

https://github.com/a-bdellatif/frequencydivider

verilog code for frequency divider circuit implemented with verilog hdl

digital-design fpga frequency-divider hardware-description-language hdl verilog

Last synced: 03 Feb 2025

https://github.com/dyna-bytes/fpga_winter_internship_2020

[Korea University Elementary Particle Physics Lab] Hardware control research using FPGA

fpga rtl verilog vhdl

Last synced: 30 Jan 2025

https://github.com/mummanajagadeesh/i2c-protocol-verilog

Verilog Implementation of I2C Protocol using Finite State Machine (FSM) design

finite-state-machine fpga fsm i2c i2cprotocol verilog verilog-hdl verilog-project xilinx xilinx-vivado

Last synced: 25 Jan 2025

https://github.com/chayashri2308/parking_management

Parking Management System using Verilog, to identify the occupied and vacant space in a parking lot.

fpga verilog

Last synced: 31 Jan 2025

https://github.com/chayashri2308/vending_machine

A simple Vending Machine design for only one product using Verilog. The user can enter three different currency notes and based on the price of the product, the machine dispenses the product and gives the change.

verilog

Last synced: 31 Jan 2025

https://github.com/rehankarthikchandralal/implementation-of-a-configurable-neural-processing-unit-with-input-and-weight-stationary-dataflows

Used Verilog to design an entire NPU that supports two different kinds of dataflows to enable data reuse in order to reduce power consumption and resource utilization

neural-network-hardware verilog

Last synced: 09 Feb 2025

https://github.com/vgalovic/hdl_examples

A collection of VHDL and Verilog examples organized by language and practice section, with setup.tcl files for easy Vivado setup. These examples reflect my FPGA development practice and learning.

tcl verilog vhdl vivado

Last synced: 03 Jan 2025

https://github.com/delhatch/flipdot_video

Video streaming from a camera to a 58x24 pixel flipdot display. See the two flipdot_display*.mp4 videos. All processing in Verilog RTL (no softcore uP).

altera de2-115 flipdot flipdots fpga verilog

Last synced: 13 Jan 2025

https://github.com/m13253/sbmips

Naïve MIPS32-like CPU design with pipeline on a Xilinx FPGA

fpga mips mips32 verilog

Last synced: 01 Feb 2025

https://github.com/abdallahabusidu/cmp305-introduction-verilog

introduction to Verilog in Integrated Circuit Design And VLSI technology

verilog verilog-code verilog-hdl verilog-project

Last synced: 06 Feb 2025

https://github.com/ain1084/dual_clock_buffer

Dual clock buffer for modules connected by valid-ready protocol

protocol-buffers verilog

Last synced: 13 Feb 2025

https://github.com/sauravmaheshkar/verilog-template

❄️ Template for Verilog Projects using iverilog and gtkwave (nix devShell supported)

hardware-description-language template-project verilog verilog-template vhdl

Last synced: 01 Feb 2025

Verilog Awesome Lists
awesome-hdl 121 awesome-open-hardware-verification 44 ASIC-Design-Roadmap 83 VHDL-Guide 287 CPLD-Guide 287
Verilog Categories
OpenCL Tools, Libraries and Frameworks 139 C/C++ Tools, Libraries and Frameworks 80 C/C++ Learning Resources 68 MATLAB Tools, Libraries, Frameworks 66 Firmware Tools, Libraries, and Frameworks 56 Assembly Learning Resources 36 MATLAB Learning Resources 34 Meta HDL and Transpilers 32 Projects and IPs 31 Firmware Learning Resources 28 Verilog/SystemVerilog Learning Resources 25 Verilog/SystemVerilog Tools 24 Frameworks: 23 OpenCL Learning Resources 22 HLS 16 Tutorials and Courses 💬[Intro](./Tutorials%20and%20Courses/README.md) 15 Tutorials and Courses 15 PSS : Portable test and Stimulus Standard 14 Awesome Awesome ⭐ 12 HDL simulators and compilers 9