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Verilog
Verilog is a widely-used hardware description language (HDL) that enables designers to model, simulate, and synthesize digital circuits. It provides a text-based format for specifying the structure and behavior of electronic systems, making it easier to design complex hardware components such as microprocessors, memory, and communication devices.
- GitHub: https://github.com/topics/verilog
- Wikipedia: https://en.wikipedia.org/wiki/Verilog
- Aliases: hdl, hardware-description-language,
- Last updated: 2025-01-09 00:31:35 UTC
- JSON Representation
https://github.com/brlin-tw/clean-filter-for-verilog
Clean your Verilog design code!
bash clean-filter filter git git-attributes istyle vdent verilog
Last synced: 21 Nov 2024
https://github.com/valaphee/redsynth
Generate redstone circuits out of Verilog.
bukkit-plugin fpga minecraft redstone synthesis verilog
Last synced: 07 Jan 2025
https://github.com/m13253/sbmips
Naïve MIPS32-like CPU design with pipeline on a Xilinx FPGA
Last synced: 05 Dec 2024
https://github.com/melchisedech333/verilog-experiments
:space_invader: My studies with Verilog and notions of digital systems.
digital-system-design digital-systems digital-systems-design digital-systems-fundamentals hdl icarus-verilog verilog verilog-code verilog-examples verilog-hdl verilog-project
Last synced: 08 Dec 2024
https://github.com/jamesits/verilog-basic-blocks
数电作业
verilog verilog-components xilinx-ise
Last synced: 05 Dec 2024
https://github.com/jn513/baby-risco-5
Multi-cycle RISC-V processor with RV32E implementation
riscv riscv32 riscv32e verilog verilog-hdl
Last synced: 15 Dec 2024
https://github.com/asankasovis/eight_bit_computer
🎛️ FPGAs are an interesting invention that is expected to revolutionize the digital industry. This series will focus on building the 8-bit computer that Ben Eater built on his youtube channel. However, it will be done not with actual chips and hardware, but with Verilog code and FPGA simulations.
8bit beneater computer fpga fpga-programming verilog
Last synced: 08 Dec 2024
https://github.com/jn513/estudos_verilog
Exemplos feito em verilog para estudos
fpga fpga-programming hardware verilog verilog-code verilog-hdl
Last synced: 15 Dec 2024
https://github.com/vgalovic/hdl_examples
A collection of VHDL and Verilog examples organized by language and practice section, with setup.tcl files for easy Vivado setup. These examples reflect my FPGA development practice and learning.
Last synced: 03 Jan 2025
https://github.com/tomarus/midirouter
CMOD-A7 FPGA MIDI Merger/Router/Switch.
Last synced: 15 Dec 2024
https://github.com/xtrinch/icestick-fpga-example
Example project for Lattice icestick fpga
fpga icestorm-toolchain verilog
Last synced: 21 Dec 2024
https://github.com/brosnanyuen/tt07-neuromorphic-asic-with-96-neurons
Neuromorphic ASIC with 96 neurons on Tiny Tapeout 7
asic computational-neuroscience deep-learning fpga machine-learning neural-network neuromorphic neuromorphic-computing pcb snn spiking-neural-networks tinytapeout verilog
Last synced: 13 Nov 2024
https://github.com/anuragnatoo/ele301p
VLSI System Design Practice Lab
activity-factors practice-lab python python-application test-bench verilog vlsi
Last synced: 12 Nov 2024
https://github.com/bucknalla/warc_fusesoc
WARC Open Fusesoc Cores Repository
hls ip migen open-cores verilog
Last synced: 09 Jan 2025
https://github.com/byte-me404/tt-ps2-morse-encoder
Custom ASIC design which decodes a PS/2 keyboard, furthermore it encodes and outputs the data as morse code
asic morse-code ps2-keyboard tinytapeout verilog
Last synced: 05 Jan 2025
https://github.com/tmahlburg/mriscv
simple, modular rv32i implementation (WIP)
risc-v riscv riscv32 rv32i verilog verilog-hdl
Last synced: 16 Nov 2024
https://github.com/yaxsomo/iris_cubesat
This Repository is dedicated to FPGA development of the IRIS CubeSat
aerospace cubesat fpga free-space-optical-communiucation satellite verilog vhdl vivado xilinx
Last synced: 12 Nov 2024
https://github.com/francoriba/alu-uart-basys3
UART modules interface using Verilog for the Basys3 board (Digilent). Computer Architecture 2023. FCEFyN, UNC, Argentina
arquitectura-de-computadores basys3-fpga computerarchitecture fcefyn hardwaredescription uart unc verilog
Last synced: 12 Nov 2024
https://github.com/dvvcz/cpe-133
icarus-verilog iverilog systemverilog verilog vivado
Last synced: 05 Jan 2025
https://github.com/jasonbrave/microsoc
RISC-V SoC
microcontroller risc-v riscv soc system-on-chip systemverilog uart verilog
Last synced: 20 Dec 2024
https://github.com/sgq995/rc4-de0-nano-soc
It's a cryptoprocessor that implements de RC4 algorithm
de0-nano-soc fpga fpga-soc rc4 verilog
Last synced: 07 Jan 2025
https://github.com/abtinz/logic-circuits-final-project
Aut Logic Circuits Finall Project Fall 1400
Last synced: 12 Nov 2024
https://github.com/liu42/pipeline
《计算机组成原理》课程设计，基于 MIPS 系统的流水线 CPU 设计
architecture computer-architecture course-project cpu fpga homework-project mips mips-architecture mips-processor pipeline verilog
Last synced: 23 Nov 2024
https://github.com/standardsemiconductor/veldt-blinker-verilog
VELDT blinker example with verilog
Last synced: 12 Nov 2024
https://github.com/skpro-glitch/riscv-processor-asic
This is a basic RISC-V based processor under development. It follows the 32-bit Integer ISA.
asic asic-design asic-verification fpga hardware-designs open-source openlane openlane-flow processor-architecture processor-design risc-v riscv32 verilog verilog-hdl vlsi vlsi-design
Last synced: 20 Dec 2024
https://github.com/tm90/verilogmodules
generic Verilog modules for reuse...
generic-verilog-modules systemverilog verilog
Last synced: 13 Nov 2024
https://github.com/sofiavalos/verilog_ethernet_10g_pcs
Bloques y bancos de pruebas PCS para Ethernet 10G.
Last synced: 05 Jan 2025
https://github.com/marialmeida1/study-ac
Atividades de Arquitetura de Computadores 1
arquitetura-de-computadores java python verilog
Last synced: 05 Jan 2025
https://github.com/ain1084/dual_clock_buffer
Dual clock buffer for modules connected by valid-ready protocol
Last synced: 20 Dec 2024
https://github.com/aditeyabaral/up-down-counter
A simple up-down counter made using icarus verilog as a part of the Digital Design and Computer Organization course (UE18CS201) at PES University.
counter digital-design icarus-verilog logic-programming verilog verilog-project
Last synced: 16 Nov 2024
https://github.com/rithwikksvr/verilog-snake-game
Last semester we made a Snake Game implemented on Hardware. For this Purpose we used Basys 2 Spartan-3E FPGA, 7x5 LED Matrix and Verilog Programming.
Last synced: 13 Nov 2024
https://github.com/vivekadi/fpga_verilog_interfacing
Interfacing peripherals to FPGA
fpga interfacing keypad4x4 labs motor-controller singal-generator spartan6 verilog xilinx
Last synced: 14 Nov 2024
https://github.com/chaseruskin/verb
An approachable testing framework for digital hardware
framework python simulation system-verilog testing verification verilog vhdl
Last synced: 14 Nov 2024
https://github.com/kar-dim/icsd-digitalsystems
Some Verilog projects, implemented as part of my university coursework (2013-2019, Information and Communications Systems Engineering, University of the Aegean).
Last synced: 04 Jan 2025
https://github.com/marceldobehere/goofy-cpu-verilog
cpu cpu-simulator goofy goofy-cpu sim verilog
Last synced: 04 Jan 2025
https://github.com/quentinwach/computer-engineering
📝 Notes on computer engineering. From application to custom computer design.
book computer-architecture course cpu cpu-architecture documentation gtkwave hack hack-computer icarus icarus-verilog iverilog logisim nand2tetris nand2tetris-assignments nand2tetris-projects nand2tetris-solutions recources verilog
Last synced: 13 Nov 2024
https://github.com/abdallahabusedo/cmp305-introduction-verilog
introduction to Verilog in Integrated Circuit Design And VLSI technology
verilog verilog-code verilog-hdl verilog-project
Last synced: 13 Dec 2024
https://github.com/ghazaleze/microblaze-equation-solver
for solving cubic equation
Last synced: 05 Jan 2025
https://github.com/the-pinbo/risc-spm
This project involves the development and enhancement of a RISC Stored-Program Machine (RISC SPM), based on the architecture detailed in "Advanced Digital Design with the Verilog HDL" by Michael D. Ciletti.
computer-architecture riscv verilog
Last synced: 25 Dec 2024
https://github.com/muhammadtalhasami/rtl_practice
This repository contain basic verilog codes which include the implementation of DLD (digital logic desgin ) circuits.
100daysofrtl hardware-coding muhammadtalhasami-github- rtl testbench verilog verilog-practice vhdl
Last synced: 25 Dec 2024
https://github.com/antonioberna/computer-architecture-engineering
Computer Architecture Engineering (Assembly and C)
assembly c computer-architecture digital verilog vhdl
Last synced: 13 Nov 2024
https://github.com/jgroman/fpga-tangprimer25k-experiments
Learning digital design with Tang Primer 25K
Last synced: 19 Nov 2024
https://github.com/drom/vpreproc
Verilog preprocessor bindings for Node.js
napi nodejs preprocessor verilog
Last synced: 18 Dec 2024
https://github.com/eshansurendra/uart-fpga
This repository documents a project undertaken as part of the EN2111 Electronic Circuit Design module at the University of Moratuwa, focusing on the implementation of a UART communication link between two FPGA boards.
digital-design embedded-systems fpga quartus-prime systemverilog-hdl testbench uart verilog
Last synced: 17 Nov 2024
https://github.com/blagojeblagojevic/vga_verilog
Implementation of a vga interface on a Basys 3 FPGA
Last synced: 21 Dec 2024
https://github.com/sauravmaheshkar/verilog-template
❄️ Template for Verilog Projects using iverilog and gtkwave (nix devShell supported)
hardware-description-language template-project verilog verilog-template vhdl
Last synced: 06 Dec 2024
https://github.com/alyssonmach/sistema-seguranca-residencial
Projeto final da disciplina Laboratório de Circuitos Lógicos - Sistema de Segurança Residencial.
logic-circuit logic-gates logisim project ufcg verilog
Last synced: 24 Dec 2024
https://github.com/xilover/iot-and-edge-computing
Hands-on learning experience in IoT, edge computing, and embedded systems using a variety of platforms such as microcontrollers (nRF, STM32, ESP32), FPGAs (Xilinx), and SoCs (Raspberry Pi, Zynq).
aws-iot azure-iot ble circuit-design edge-computing esp32 fpga iot mqtt nrf pynq-z2 raspberry-pi rtos stm32 system-on-chip verilog vhdl vivado xilinx xilinx-zynq
Last synced: 18 Dec 2024
https://github.com/rauhul/ece385
Digital Systems Laboratory UIUC FA 2016
altera fpga quartus-prime systemverilog verilog
Last synced: 02 Dec 2024
https://github.com/pavlostzitzos/hdls-intro
SystemVerilog , Verilog , Verilog-A , Verilog-AMS tutorial
verilog verilog-hdl verilog-testbenches vhdl
Last synced: 24 Dec 2024
https://github.com/weisrc/nesv
NESystem Verilog
basys3 emscripten emulator fpga nes systemverilog verilator verilog vivado webassembly
Last synced: 23 Dec 2024
https://github.com/shuregg/miet-interfaces
Interfaces of computing systems
interfaces protocols verilog verilog-hdl
Last synced: 13 Dec 2024
https://github.com/ain1084/machxo2_serial_to_spdif_transmitter
Serial (LPCM) to S/PDIF transmitter. Using MachXO2 (1200HC QFN32).
Last synced: 20 Dec 2024
https://github.com/ain1084/audio_level_meter
This is an audio level meter implemented using Verilog HDL.
audio machxo2 verilog visualization
Last synced: 20 Dec 2024
https://github.com/akafael/verilog-sandbox
selflearning tutorial-exercises verilog
Last synced: 29 Nov 2024
https://github.com/jackson-nestelroad/verilog-mips-processor
Single-cycle 32-bit MIPS processor implemented in SystemVerilog.
Last synced: 01 Dec 2024
https://github.com/chili-chips-ba/uberclock
Digital systems are clocked. This project is about constructed a high-Q clock by simmering an ordinary quartz in a heavy numerical "secret sauce" that is fully open to the public.
clock-generator crystal dsp fpga risc-v rtl stratum-2 verilog
Last synced: 06 Dec 2024
https://github.com/birdybro/nand2tetris_mister
Nand2Tetris for MiSTer (as a learning experience for me).
hdl mister misterfpga tetris verilog verilog-hdl
Last synced: 05 Dec 2024
https://github.com/ethanuppal/berkeley-hardfloat
Downstream hardfloat with custom patches
berkeley floating-point verilog
Last synced: 14 Dec 2024
https://github.com/niqzart/pylohd
High-level framework for simplification and systematization of processes in electronic design
converter hdl python thesis-project verilog
Last synced: 06 Dec 2024
https://github.com/kenny2github/verilog-cpu
A very rudimentary and haphazard CPU created in Verilog.
Last synced: 20 Dec 2024
https://github.com/orcalinux/computer-organization-and-architecture
Verilog code examples and materials for Computer Organization.
8086-microprocessor computer-architecture computer-organization modelsim pic programmable-interrupt-controller qu synthesis-project verilog
Last synced: 20 Dec 2024
https://github.com/sofiavalos/verilog_ethernet_10g_mac
Bloques y bancos de pruebas MAC para Ethernet 10G.
Last synced: 12 Dec 2024
https://github.com/risto97/socmake
Build system for RTL and SoC designs
cmake cpu hardware rtl simulation systemc systemonchip systemrdl verilog
Last synced: 21 Dec 2024
https://github.com/markmll/todaystart-a153
As-shipped demo for the Altera Cyclone TodayStart-A153 board. Requires Quartus-II 10.1 SP1 minimum.
Last synced: 21 Dec 2024
https://github.com/samiyaalizaidi/pipelined-risc-v-processor
A Pipelined RISC-V Processor with forwarding support and hazard detection.
assembly computer-architecture pipelining processor processor-architecture risc-v verilog vivado
Last synced: 16 Nov 2024
https://github.com/saifalomari99/fpga_projects_saifalomari
This Repository is to showcase Saif Alomari's FPGA projects. Includes 25 high-level FPGA projects in various HDLs.
Last synced: 28 Dec 2024
https://github.com/niw/chisel_test
A simple Chisel test project for myself to learn Chisel and FPGA.
chisel3 fpga orangecrab scala tinyfpga verilog
Last synced: 06 Jan 2025
https://github.com/rainingcomputers/srp16
SRP16 is free and open ISA for 16-bit CPUs and Microcontrollers.
cpu instruction-set-architecture isa isa-specification microcontrollers open-embedded open-isa risc soft-core verilog
Last synced: 21 Dec 2024
https://github.com/limpix31/tangmega138kpro-blink
fpga hardware-design hdl system-verilog verilog
Last synced: 07 Jan 2025
https://github.com/carlkidcrypto/digital-systems-engineering
A repo for ECE 440 (Digital Systems Engineering) class projects
systemverilog verilog xilinx-vivado zynq
Last synced: 16 Dec 2024
https://github.com/bipinoli/vericlash
Implementation of bunch of circuits in Haskell (Clash) and Verilog to learn and compare them
Last synced: 21 Dec 2024
https://github.com/mohamad-shosha/alu-verilog-proteus
This 4-bit ALU design project has been implemented as part of the [Computer Aided Design] in the university , where we applied Verilog for hardware design and Proteus for simulation.
Last synced: 28 Dec 2024
https://github.com/abdullahmaqbool22/arithmetic-logic-unit-alu
A final semester project for Digital Logic Data.
Last synced: 29 Dec 2024
https://github.com/mohammadmahdi-abdolhosseini/digital-logic-courses
Digital Systems 1 & 2 + Digital Systems Laboratory 1 + Digital Electronics Circuit +Microprocessor Based and Embedded Design courses projects
Last synced: 07 Jan 2025
https://github.com/eonu/fpga
Hardware implementations for basic digital circuit designs in Verilog with a Xilinx Artix-7 FPGA chip on a Digilent Basys 3 development board.
artix-7 basys3 circuits digital-design fpga hardware hardware-designs hdl simulation testbench verilog vivado
Last synced: 29 Dec 2024
https://github.com/memgonzales/hdl-flip-flop
Compilation of Verilog behavioral models and test benches for the four types of flip-flops (SR, JK, D, and T)
behavioral-modeling computer-architecture flip-flop sequential-circuits verilog
Last synced: 19 Nov 2024
https://github.com/woolseyworkshop/article-getting-started-with-the-tinyfpga-bx
Getting Started With The TinyFPGA BX Article Resources
electronics programming tinyfpga-bx verilog
Last synced: 29 Dec 2024
https://github.com/woolseyworkshop/article-creating-a-configurable-multifunction-logic-gate-in-verilog
Creating A Configurable Multifunction Logic Gate In Verilog Article Resources
Last synced: 29 Dec 2024
https://github.com/mongshil553/digital-engineering-verilog-assignments
Sophomore 2021 1st Semester Digital Engineering Verilog Assignments
fpga-programming verilog xilinx-vivado
Last synced: 14 Nov 2024
https://github.com/karagultm/datapath
The project involved extending the processor to support six new instructions: brv, jmxor, nori, blezal, jalpc, and baln. This required modifications to the control logic, the addition of new multiplexers, and the inclusion of status register flags to handle the specific behaviors of these instructions.
mips mips-architecture mips-assembly verilog
Last synced: 24 Dec 2024
https://github.com/rpigor/tpsim
TPSim (Timing and Power Simulator) is a gate-level circuit simulator with timing and power estimation capabilities
eda power-analysis simulator timing-analysis verilog
Last synced: 06 Jan 2025
https://github.com/youseftareq33/digital_buildcombinationalcircuit_2
Using Verilog HDL on Quartus application build combinational circuit
Last synced: 24 Dec 2024
https://github.com/roscibely/arithmetic-logic-unit
A simple arithmetic logic unit (ALU) with System verilog
Last synced: 21 Nov 2024
https://github.com/yvesemmanuel/microwave
second project - Digital System
digital-systems verilog verilog-components verilog-project
Last synced: 16 Nov 2024
https://github.com/yvesemmanuel/introduction_verilog
digital systems
digital-systems verilog verilog-components verilog-project
Last synced: 16 Nov 2024