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Verilog
Verilog is a widely-used hardware description language (HDL) that enables designers to model, simulate, and synthesize digital circuits. It provides a text-based format for specifying the structure and behavior of electronic systems, making it easier to design complex hardware components such as microprocessors, memory, and communication devices.
- GitHub: https://github.com/topics/verilog
- Wikipedia: https://en.wikipedia.org/wiki/Verilog
- Aliases: hdl, hardware-description-language,
- Last updated: 2025-01-09 00:31:35 UTC
- JSON Representation
https://github.com/jn513/grande-risco-5
Processador RISC-V multi ciclo com implementação RV32I construído em alguns dias de folga.
arquitetura fpga risc-v riscv riscv32 verilog verilog-hdl
Last synced: 15 Dec 2024
https://github.com/cepdnaclk/e16-co502-rv32im-pipeline-implementation-group1
The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pipeline CPU supports the entire RV32IM ISA which contains 45 instructions. The designed pipeline CPU was implemented using behavioral modeling in verilogHDL and icarus Verilog was used compile and simulate. gtkWave was used to observe the behavior.
computer-architecture pipeline risc-v rv32im verilog
Last synced: 12 Nov 2024
https://github.com/jn513/pequeno-risco-5
Processador RISC-V de ciclo único com implementação RV32I construído em alguns dias de folga.
arquitetura risc-v riscv riscv32 verilog verilog-hdl
Last synced: 15 Dec 2024
https://github.com/algosup/2024-2025-project-1-fpga-team-7
This version of the "Frogger" game is made using a "go-board" and the "verilog" programming language. It takes only the road part of the original game and is made to be used with a vga screen.
frogger frogger-game go-board-game verilog
Last synced: 16 Nov 2024
https://github.com/eyantra698sumanto/digital-design-on-fpga
This repo contains documentation of the "VSD Open Digital-Design-on-FPGA" tutorial.
fpga makerchip systemverilog tl-verilog verilog virtual-fpga vsd
Last synced: 09 Jan 2025
https://github.com/calint/tang-nano-20k--riscv
riscv rv32i tang-nano-20k verilog
Last synced: 10 Jan 2025
https://github.com/gogolb/ee175
EE 175 Senior Design. Multibaseline Stereo Camera
computer-vision matlab ov7670 senior-design slam stereo-vision university-course university-project verilog vivado xilinx zynq
Last synced: 01 Dec 2024
https://github.com/sped0n/ada
An Artix 7 based dual channel oscilloscope.
artix-7 ft232h oscilloscope verilog xc7a35t
Last synced: 24 Dec 2024
https://github.com/raleighlittles/basys3countdownclock
Extremely basic countdown clock project for the Basys 3 FPGA development board.
basys-3 basys3 fpga hdl seven-segment-display verilog vivado xdc xilinx
Last synced: 28 Nov 2024
https://github.com/akhilrai28/gravity-accelerator
This project implements a gravity accelerator using Verilog and Vivado. It simulates the physics of gravitational acceleration, calculating velocity and position over time within a digital circuit environment. The project includes testbenches and waveform analysis to ensure accurate simulation and performance.
digital-simulation fpga gravity-algorithm gravity-model gravity-simulation hardware hardware-acceleration hardware-designs physics-simulation testbench verilog vivado
Last synced: 15 Dec 2024
https://github.com/zannatul-naim/digital-system-design
Digital System Design Lab Codes using Verilog
adder d-flipflop flipflop full-adder half-adder jk-flipflop ripple-carry-adder t-flipflop verilog
Last synced: 26 Dec 2024
https://github.com/can-lehmann/hdl.cpp
Register-transfer Level Intermediate Representation
cpp fpga intermediate-representation rtl verilog
Last synced: 24 Oct 2024
https://github.com/abhishek010397/programming-risc-v
Design of RISC V CPU Core
advanced-computer-architecture microprocessor multithreading python3 risc-v verilog
Last synced: 23 Dec 2024
https://github.com/dvvcz/viva
Experimental cli to create HDL projects using Vivado, outside of their IDE.
cli hardware hdl package-manager rust systemverilog verilog vivado
Last synced: 05 Jan 2025
https://github.com/yugr/parmatch
A simple script for finding unbound parameters in Verilog module instantiations.
static-analysis static-analyzer verilog
Last synced: 27 Dec 2024
https://github.com/hashirshoaeb/verilog-codes
This repository is to help macOS and linux users who have just started learning verilog.
assignment getting-started lab-tasks learning-verilog linux-users macos scansion verilog vscode vscode-plugin
Last synced: 06 Jan 2025
https://github.com/donn/swiftlog
An IcarusVerilog VPI bridge for the Swift Programming Language.
Last synced: 28 Nov 2024
https://github.com/kaushalmodi/nim-systemverilog-vpi
Using Nim to interface with Verilog and SystemVerilog test benches via VPI
1364-2005 1800-2017 c cpp nim pli systemverilog verilog vpi
Last synced: 15 Nov 2024
https://github.com/cw1997/graphical_card
a graphical card for displaying text on VGA text mode by D-Sub port
graphical-programming hardware hardware-designs systemverilog-simulation verilog verilog-project
Last synced: 28 Nov 2024
https://github.com/aliiimaher/mips-verilog
MIPS architecture implemented in Verilog.
mips mips-architecture pipeline-mips verilog
Last synced: 13 Nov 2024
https://github.com/gyeonghokim/riscv_core
building 32bit risc-v core and Machine Learning for Branch Prediction
Last synced: 29 Dec 2024
https://github.com/bugenzhao/mips
👨🏻💻 Pipelined MIPS I CPU with 49 instructions & multiplication & direct-mapped cache in Verilog.
Last synced: 23 Nov 2024
https://github.com/ain1084/audio_echo_effect
Simple echo effect implementation with digital audio processing.
audio-processing i2s-audio lattice-fpga verilog
Last synced: 20 Dec 2024
https://github.com/pvgupta24/cse-labs
Dump for CSE Lab assignments and programs
algorithms c computer-architecture cpp data-structures mips opengl verilog
Last synced: 06 Jan 2025
https://github.com/samridhisainii/digitaldesign
These are the question of digital design lab from our subject digital design lab which were done in lab
Last synced: 29 Nov 2024
https://github.com/amirreza81/digital-systems-design
Digital Systems Design - Spring 2023 - Sharif University of Technology
assembly digital-system-design verilog
Last synced: 05 Jan 2025
https://github.com/liu42/processor
《计算机组成原理》课程设计，基于 MIPS 的流水线 CPU 系统设计。
architecture computer-architecture course-project cpu fpga homework-project mips mips-architecture mips-processor pipeline verilog
Last synced: 21 Dec 2024
https://github.com/aben20807/computer_organization
1052_計算機組織 COMPUTER ORGANIZATION
cache cpu datapath pipeline single-cycle verilog
Last synced: 16 Nov 2024
https://github.com/risto97/cascade_classifier
Python, C, RTL implementation of Viola Jones cascade classifier, using pretrained model from opencv.
face-detection fpga object-detection pygears python verilog viola-jones
Last synced: 21 Dec 2024
https://github.com/yugr/gatecheck
Yet another Verilog static analyzer
clock-g gating static-analysis static-analyzer verilog
Last synced: 27 Dec 2024
https://github.com/hywooo/docker-bsv-wsl2
🐋Docker for Bluespec SystemVerilog (BSV) on WSL2, compatible with WangXuan95/BSV_Tutorial_cn. 适用于BSV中文教程的Docker BSV （WSL2）环境。
bluespec-systemverilog bsv docker dockerfile packages systemverilog verilog vivado
Last synced: 29 Oct 2024
https://github.com/kigawas/mipscpu
A single cycle CPU running on Xilinx Spartan 6 XC6LX16-CS324, supporting 31 MIPS instructions.
educational-project mips verilog
Last synced: 12 Nov 2024
https://github.com/eomielan/16-bit-risc-machine
16-bit CPU architecture implementation and verification using SystemVerilog
cpu-architecture systemverilog verilog
Last synced: 30 Dec 2024
https://github.com/alyssonmach/logic-circuits
Simulations made in the UFCG logic circuit laboratory.
laboratory logic-circuit logisim quartus ufcg verilog
Last synced: 24 Dec 2024
https://github.com/muhammadtalhasami/sv_verilator
System verilog learning journey. Here in this repo you learn about how to write system verilog test bench using verilator tool a c++ test bench. Verilator is basically a 2 state tool .
system-verilog-testbench systemverilog testbench verification verilator- verilator-testbench verilog verilog-hdl
Last synced: 06 Nov 2024
https://github.com/algosup/2024-2025-project-1-fpga-team-4
Recreating the arcade game Frogger using FPGA and Verilog
fpga retrogaming school-project verilog
Last synced: 16 Nov 2024
https://github.com/bryanlimy/flappybird-verilog
Flappy-Bird-liked game in Verilog
flappy-bird flappy-bird-game verilog
Last synced: 17 Dec 2024
https://github.com/akhilrai28/alarm-clock
This project implements a fully functional digital alarm clock using Verilog and Vivado. The design includes features such as setting the time, alarm functionality, and real-time clock display. The project simulates clock timing and alarm triggers, with testbenches for verifying accuracy and reliability on FPGA.
alarm alarm-clock clock fpga hardware real-time simulation testbench verilog vivado
Last synced: 15 Dec 2024
https://github.com/ehsanshahbazii/digital-vlsi-system-design-projects
سورس کد پروژه های درس طراحی سیستم های دیجیتال برنامه پذیر دانشگاه تبریز مقطع کارشناسی رشته مهندسی کامپیوتر
verilog verilog-code verilog-components verilog-project vlsi
Last synced: 10 Nov 2024
https://github.com/lebrancconvas/verilog-playground
Verilog Playground.
digital-electronics logic-gates verilog
Last synced: 08 Jan 2025
https://github.com/meetps/ee-214
VHDL and Verilog Codes for Digital Lab.
digital-logic fpga verilog vhdl
Last synced: 04 Jan 2025
https://github.com/ashkan-khd/conways-game-of-life-verilog
An easy approach for Conway's Game Of Life with Verilog HDL
conways-game-of-life conways-game-of-life-verilog game-of-life game-of-life-verilog testbench verilog verilog-game-of-life verilog-hdl
Last synced: 20 Dec 2024
https://github.com/viktor-prutyanov/fpga-ir
IR receiver with UART interface
fpga ir-receiver remote-control verilog
Last synced: 12 Dec 2024
https://github.com/pconst/xilinx_max_power
Creating dummy load to dissipate maximum power in Xilinx FPGA
arty board cooling development digilent fpga power shift-register soc systemverilog test ultrascale verilog xilinx zinq
Last synced: 12 Nov 2024
https://github.com/urish/tt05-silife-8x8
Game of Life in Silicon (8x8)
game-of-life tiny-tapeout verilog
Last synced: 12 Nov 2024
https://github.com/yasnakateb/pipelinedmips
🔮 A 16-bit MIPS Processor Implementation in Verilog HDL
cpu icarus-verilog iverilog mips mips-pipeline mips-processor pipeline verilog verilog-hdl
Last synced: 19 Nov 2024
https://github.com/pirate-emperor/cipherx
CipherX is a verification project for Advanced Encryption Standard (AES-128) using Universal Verification Methodology (UVM). It leverages Verilog, SystemVerilog, and Python to ensure robust encryption algorithm validation, integrating comprehensive UVM components and tests.
aes-128 cryptography cryptography-algorithms dataencryption dataencryptionstandards digitaldesign encrytption hardwareverification python security testing-framework uvm verification verilog
Last synced: 04 Dec 2024
https://github.com/shyamal-anadkat/the-11-of-us
adc ece551 flight-controller hdl integrator quadcopter synthesis system-verilog uart verilog vhdl
Last synced: 16 Dec 2024
https://github.com/barrettotte/subarashii-cpu
A 16-bit RISC CPU inspired by MIPS. I designed this to learn more about computer architecture/organization.
cpu homebrew risc-processor verilog verilog-cpu
Last synced: 09 Dec 2024
https://github.com/sinakarvandi/hardware-design-stack
The source codes used in the blog post available at: https://rayanfam.com/topics/hardware-design-stack/
asic asic-design chisel chisel3 fpga gtkwave modelsim netlist openlane openram verilator verilog vhdl vitis vitis-hls vivado vivado-hls
Last synced: 17 Nov 2024
https://github.com/kyori19/verilog-otp
VerilogHDL implementation of One-Time Password Algorithm (HOTP)
hotp onetimepassword systemverilog verilog verilog-hdl
Last synced: 17 Nov 2024
https://github.com/engineeringsoftware/hdlp
Code and data for "On the Naturalness of Hardware Descriptions" in ESEC/FSE'20
deep-learning hardware-description-language machine-learning naturalness pytorch systemverilog verilog vhdl
Last synced: 18 Nov 2024
https://github.com/byte-me404/jku-tt06-ps2-morse-encoder
Custom ASIC design which decodes a PS/2 keyboard, furthermore it encodes and outputs the data as morse code
asic ps2-keyboard tinytapeout verilog
Last synced: 05 Jan 2025
https://github.com/z4yx/thinpad-controller-zynq
RTL project for the controller SoC on Thinpad
Last synced: 01 Dec 2024
https://github.com/yahia3200/spi-protocol-implementation-using-verilog
Implementing SPI interface using Verilog
Last synced: 21 Nov 2024
https://github.com/phillbush/tbgen
Testbench generator in AWK for Verilog modules
awk testbench testbench-generator testbench-generator-verilog verilog
Last synced: 22 Nov 2024
https://github.com/cpehle/cascade
Cycle based C++ hardware simulation infrastructure
Last synced: 15 Dec 2024
https://github.com/alokmenghrajani/adventofcode2018
Advent of Code 2018. Solutions using Verilog + icestick fpga! ☃️🎄🎁🦌🎅
2018 advent-of-code-2018 advent-of-code-2018-fpga adventofcode adventofcode2018 fpga solutions upping-the-ante verilog
Last synced: 25 Nov 2024
https://github.com/tm90/verilogmodules
generic Verilog modules for reuse...
generic-verilog-modules systemverilog verilog
Last synced: 13 Nov 2024
https://github.com/aditeyabaral/up-down-counter
A simple up-down counter made using icarus verilog as a part of the Digital Design and Computer Organization course (UE18CS201) at PES University.
counter digital-design icarus-verilog logic-programming verilog verilog-project
Last synced: 16 Nov 2024
https://github.com/sauravmaheshkar/verilog-template
❄️ Template for Verilog Projects using iverilog and gtkwave (nix devShell supported)
hardware-description-language template-project verilog verilog-template vhdl
Last synced: 06 Dec 2024
https://github.com/chayashri2308/parking_management
Parking Management System using Verilog, to identify the occupied and vacant space in a parking lot.
Last synced: 04 Dec 2024
https://github.com/tomarus/midirouter
CMOD-A7 FPGA MIDI Merger/Router/Switch.
Last synced: 15 Dec 2024
https://github.com/kareimgazer/pci_target_device
Verilog simulation for a Target Device on a PCI bus with read and write transactions.
pci pci-devices verilog xilin xilinx-vivado
Last synced: 08 Dec 2024
https://github.com/chayashri2308/vending_machine
A simple Vending Machine design for only one product using Verilog. The user can enter three different currency notes and based on the price of the product, the machine dispenses the product and gives the change.
Last synced: 04 Dec 2024
https://github.com/wpmed92/takerisc
A RISC-V RV32I Core written in TL-Verilog
hardware riscv riscv32 tl-verilog verilog
Last synced: 09 Dec 2024
https://github.com/marialmeida1/study-ac
Atividades de Arquitetura de Computadores 1
arquitetura-de-computadores java python verilog
Last synced: 05 Jan 2025
https://github.com/dineshpinto/timetagger
FPGA programming for nanosecond photon counting
c fpga fpga-programming linux photonics picosecond swig-binding verilog
Last synced: 09 Dec 2024
https://github.com/anuragnatoo/ele301p
VLSI System Design Practice Lab
activity-factors practice-lab python python-application test-bench verilog vlsi
Last synced: 12 Nov 2024
https://github.com/dineshpinto/stm32f4
Combining an FPGA, micro-controller and AWG for nanosecond photon counting
assembly awg c microcontroller photonics verilog
Last synced: 09 Dec 2024
https://github.com/lorhansohaky/ufscar
Arquivos de atividades da UFSCar
arquitetura-de-computadores banco-de-dados c cap cgi compilador compiladores computacao-grafica cpp dc estruturas-de-dados grafos ori orientacao-a-objetos paa paradigmas sistemas-operacionais ufscar verilog
Last synced: 05 Dec 2024
https://github.com/bucknalla/warc_fusesoc
WARC Open Fusesoc Cores Repository
hls ip migen open-cores verilog
Last synced: 09 Jan 2025
https://github.com/yaxsomo/iris_cubesat
This Repository is dedicated to FPGA development of the IRIS CubeSat
aerospace cubesat fpga free-space-optical-communiucation satellite verilog vhdl vivado xilinx
Last synced: 12 Nov 2024
https://github.com/asankasovis/eight_bit_computer
🎛️ FPGAs are an interesting invention that is expected to revolutionize the digital industry. This series will focus on building the 8-bit computer that Ben Eater built on his youtube channel. However, it will be done not with actual chips and hardware, but with Verilog code and FPGA simulations.
8bit beneater computer fpga fpga-programming verilog
Last synced: 08 Dec 2024
https://github.com/hiyouga/digic-experiment
BUAA CST Autumn 2018 Digital Circuit Experiment
Last synced: 05 Jan 2025
https://github.com/francoriba/alu-uart-basys3
UART modules interface using Verilog for the Basys3 board (Digilent). Computer Architecture 2023. FCEFyN, UNC, Argentina
arquitectura-de-computadores basys3-fpga computerarchitecture fcefyn hardwaredescription uart unc verilog
Last synced: 12 Nov 2024
https://github.com/bilalm04/combination-lock-fsm
Moore FSM combination lock in Verilog for DE1-SOC Board.
Last synced: 31 Dec 2024
https://github.com/andrejchoo/uart_spiflash_programmer_on_fpga
UART programmer SPI FLASH 25-series on FPGA or CPLD
fpga programmer spi-flash verilog
Last synced: 11 Dec 2024
https://github.com/sgq995/rc4-de0-nano-soc
It's a cryptoprocessor that implements de RC4 algorithm
de0-nano-soc fpga fpga-soc rc4 verilog
Last synced: 07 Jan 2025
https://github.com/abtinz/logic-circuits-final-project
Aut Logic Circuits Finall Project Fall 1400
Last synced: 12 Nov 2024
https://github.com/melchisedech333/verilog-experiments
:space_invader: My studies with Verilog and notions of digital systems.
digital-system-design digital-systems digital-systems-design digital-systems-fundamentals hdl icarus-verilog verilog verilog-code verilog-examples verilog-hdl verilog-project
Last synced: 08 Dec 2024
https://github.com/amir78729/logical-circuits-course-final-project
My Logical Circuits course Final Project - Fall98(2019) - VERILOG
Last synced: 17 Nov 2024
https://github.com/hugech38/mips
🐢 用 Verilog 实现的单周期 MIPS 指令集的 CPU，并用它来计算斐波那契数。
cpu mips mips-architecture mips-instructions mips-processor verilog vhdl
Last synced: 20 Nov 2024
