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Verilog
Verilog is a widely-used hardware description language (HDL) that enables designers to model, simulate, and synthesize digital circuits. It provides a text-based format for specifying the structure and behavior of electronic systems, making it easier to design complex hardware components such as microprocessors, memory, and communication devices.
- GitHub: https://github.com/topics/verilog
- Wikipedia: https://en.wikipedia.org/wiki/Verilog
- Aliases: hdl, hardware-description-language,
- Last updated: 2025-01-09 00:31:35 UTC
- JSON Representation
https://github.com/tomarus/midirouter
CMOD-A7 FPGA MIDI Merger/Router/Switch.
Last synced: 15 Dec 2024
https://github.com/hiyouga/digic-experiment
BUAA CST Autumn 2018 Digital Circuit Experiment
Last synced: 05 Jan 2025
https://github.com/vgalovic/hdl_examples
A collection of VHDL and Verilog examples organized by language and practice section, with setup.tcl files for easy Vivado setup. These examples reflect my FPGA development practice and learning.
Last synced: 03 Jan 2025
https://github.com/amir78729/logical-circuits-course-final-project
My Logical Circuits course Final Project - Fall98(2019) - VERILOG
Last synced: 17 Nov 2024
https://github.com/hugech38/mips
🐢 用 Verilog 实现的单周期 MIPS 指令集的 CPU，并用它来计算斐波那契数。
cpu mips mips-architecture mips-instructions mips-processor verilog vhdl
Last synced: 20 Nov 2024
https://github.com/sauravmaheshkar/verilog-template
❄️ Template for Verilog Projects using iverilog and gtkwave (nix devShell supported)
hardware-description-language template-project verilog verilog-template vhdl
Last synced: 06 Dec 2024
https://github.com/anuragnatoo/ele301p
VLSI System Design Practice Lab
activity-factors practice-lab python python-application test-bench verilog vlsi
Last synced: 12 Nov 2024
https://github.com/bucknalla/warc_fusesoc
WARC Open Fusesoc Cores Repository
hls ip migen open-cores verilog
Last synced: 09 Jan 2025
https://github.com/eshansurendra/uart-fpga
This repository documents a project undertaken as part of the EN2111 Electronic Circuit Design module at the University of Moratuwa, focusing on the implementation of a UART communication link between two FPGA boards.
digital-design embedded-systems fpga quartus-prime systemverilog-hdl testbench uart verilog
Last synced: 17 Nov 2024
https://github.com/yaxsomo/iris_cubesat
This Repository is dedicated to FPGA development of the IRIS CubeSat
aerospace cubesat fpga free-space-optical-communiucation satellite verilog vhdl vivado xilinx
Last synced: 12 Nov 2024
https://github.com/francoriba/alu-uart-basys3
UART modules interface using Verilog for the Basys3 board (Digilent). Computer Architecture 2023. FCEFyN, UNC, Argentina
arquitectura-de-computadores basys3-fpga computerarchitecture fcefyn hardwaredescription uart unc verilog
Last synced: 12 Nov 2024
https://github.com/aditeyabaral/up-down-counter
A simple up-down counter made using icarus verilog as a part of the Digital Design and Computer Organization course (UE18CS201) at PES University.
counter digital-design icarus-verilog logic-programming verilog verilog-project
Last synced: 16 Nov 2024
https://github.com/harshalmittal4/24-bit-risc-processor
Computer Architecture-MIPS Processor simulation in verilog with self developed ISA
Last synced: 19 Nov 2024
https://github.com/jasonbrave/microsoc
RISC-V SoC
microcontroller risc-v riscv soc system-on-chip systemverilog uart verilog
Last synced: 20 Dec 2024
https://github.com/melchisedech333/verilog-experiments
:space_invader: My studies with Verilog and notions of digital systems.
digital-system-design digital-systems digital-systems-design digital-systems-fundamentals hdl icarus-verilog verilog verilog-code verilog-examples verilog-hdl verilog-project
Last synced: 08 Dec 2024
https://github.com/tmahlburg/mriscv
simple, modular rv32i implementation (WIP)
risc-v riscv riscv32 rv32i verilog verilog-hdl
Last synced: 16 Nov 2024
https://github.com/valaphee/redsynth
Generate redstone circuits out of Verilog.
bukkit-plugin fpga minecraft redstone synthesis verilog
Last synced: 07 Jan 2025
https://github.com/brosnanyuen/tt07-neuromorphic-asic-with-96-neurons
Neuromorphic ASIC with 96 neurons on Tiny Tapeout 7
asic computational-neuroscience deep-learning fpga machine-learning neural-network neuromorphic neuromorphic-computing pcb snn spiking-neural-networks tinytapeout verilog
Last synced: 13 Nov 2024
https://github.com/standardsemiconductor/veldt-blinker-verilog
VELDT blinker example with verilog
Last synced: 12 Nov 2024
https://github.com/rithwikksvr/verilog-snake-game
Last semester we made a Snake Game implemented on Hardware. For this Purpose we used Basys 2 Spartan-3E FPGA, 7x5 LED Matrix and Verilog Programming.
Last synced: 13 Nov 2024
https://github.com/kareimgazer/pci_target_device
Verilog simulation for a Target Device on a PCI bus with read and write transactions.
pci pci-devices verilog xilin xilinx-vivado
Last synced: 08 Dec 2024
https://github.com/cmpark0126/mips_32bits
Implements 32bits MIPS with verilog. (18.11.25 ~ 18.12.)
Last synced: 23 Dec 2024
https://github.com/vincent-g-van/one-time-pad-fpga
64-Bits One-Time Pad on FPGA Board (Nexys 4 DDR Artix-7).
diligent nexys4 one-time-pad otp seven-segment verilog vivado
Last synced: 03 Dec 2024
https://github.com/manighazaee/cpu
CPU architecture implemented in Verilog and its assembler in Rust.
architecture assembler cpu rust verilog
Last synced: 03 Dec 2024
https://github.com/sgq995/rc4-de0-nano-soc
It's a cryptoprocessor that implements de RC4 algorithm
de0-nano-soc fpga fpga-soc rc4 verilog
Last synced: 07 Jan 2025
https://github.com/mgriebling/lola
A digital design language by Nicklaus Wirth, similar to VHDL and Verilog, but much simpler and easier to master.
circuit-compiler digital-circuit-design lola simulator swift verilog vhdl wirth
Last synced: 29 Dec 2024
https://github.com/chenqianhe/learnprofessionalbasiccoursesincomputerscience
Learn Professional Basic Courses in Computer Science计算机专业基础课程学习
assembly computer-network computer-science computer-system-structure cpp operating-system principle-of-computer-composition professional-basic-courses verilog
Last synced: 18 Nov 2024
https://github.com/chayashri2308/parking_management
Parking Management System using Verilog, to identify the occupied and vacant space in a parking lot.
Last synced: 04 Dec 2024
https://github.com/chayashri2308/vending_machine
A simple Vending Machine design for only one product using Verilog. The user can enter three different currency notes and based on the price of the product, the machine dispenses the product and gives the change.
Last synced: 04 Dec 2024
https://github.com/wpmed92/takerisc
A RISC-V RV32I Core written in TL-Verilog
hardware riscv riscv32 tl-verilog verilog
Last synced: 09 Dec 2024
https://github.com/ellisgl/driver-yl-3
Verilog code to run the YL-3 8 digit 7 segment display.
Last synced: 18 Nov 2024
https://github.com/ellisgl/addressable-debouncer-verilog
Addressable 8 SPDT debouncer in Verilog
cpld debounce debounce-button debouncing fpga verilog
Last synced: 18 Nov 2024
https://github.com/acmachado14/circuitoscombinacionais
Circuitos Combinacionais em Verilog | Trabalho pratico pra disciplina de Introdução aos Sistemas Lógicos - UFV
Last synced: 20 Nov 2024
https://github.com/rishabh-agarwal/cisc530-computersystemarchitecture
This repository contain HW and assignment for ComputerSystemArchitecture class at Harrisburg University
assignment cisc530 harrisburg homework kapila university verilog
Last synced: 28 Dec 2024
https://github.com/m13253/sbmips
Naïve MIPS32-like CPU design with pipeline on a Xilinx FPGA
Last synced: 05 Dec 2024
https://github.com/vivekadi/fpga_verilog_interfacing
Interfacing peripherals to FPGA
fpga interfacing keypad4x4 labs motor-controller singal-generator spartan6 verilog xilinx
Last synced: 14 Nov 2024
https://github.com/dineshpinto/timetagger
FPGA programming for nanosecond photon counting
c fpga fpga-programming linux photonics picosecond swig-binding verilog
Last synced: 09 Dec 2024
https://github.com/dineshpinto/stm32f4
Combining an FPGA, micro-controller and AWG for nanosecond photon counting
assembly awg c microcontroller photonics verilog
Last synced: 09 Dec 2024
https://github.com/chaseruskin/verb
An approachable testing framework for digital hardware
framework python simulation system-verilog testing verification verilog vhdl
Last synced: 14 Nov 2024
https://github.com/lorhansohaky/ufscar
Arquivos de atividades da UFSCar
arquitetura-de-computadores banco-de-dados c cap cgi compilador compiladores computacao-grafica cpp dc estruturas-de-dados grafos ori orientacao-a-objetos paa paradigmas sistemas-operacionais ufscar verilog
Last synced: 05 Dec 2024
https://github.com/brlin-tw/clean-filter-for-verilog
Clean your Verilog design code!
bash clean-filter filter git git-attributes istyle vdent verilog
Last synced: 21 Nov 2024
https://github.com/bilalm04/combination-lock-fsm
Moore FSM combination lock in Verilog for DE1-SOC Board.
Last synced: 31 Dec 2024
https://github.com/abtinz/logic-circuits-final-project
Aut Logic Circuits Finall Project Fall 1400
Last synced: 12 Nov 2024
https://github.com/andrejchoo/uart_spiflash_programmer_on_fpga
UART programmer SPI FLASH 25-series on FPGA or CPLD
fpga programmer spi-flash verilog
Last synced: 11 Dec 2024
https://github.com/blagojeblagojevic/vga_verilog
Implementation of a vga interface on a Basys 3 FPGA
Last synced: 21 Dec 2024
https://github.com/xtrinch/icestick-fpga-example
Example project for Lattice icestick fpga
fpga icestorm-toolchain verilog
Last synced: 21 Dec 2024
https://github.com/jn513/baby-risco-5
Multi-cycle RISC-V processor with RV32E implementation
riscv riscv32 riscv32e verilog verilog-hdl
Last synced: 15 Dec 2024
https://github.com/drom/vpreproc
Verilog preprocessor bindings for Node.js
napi nodejs preprocessor verilog
Last synced: 18 Dec 2024
https://github.com/quentinwach/computer-engineering
📝 Notes on computer engineering. From application to custom computer design.
book computer-architecture course cpu cpu-architecture documentation gtkwave hack hack-computer icarus icarus-verilog iverilog logisim nand2tetris nand2tetris-assignments nand2tetris-projects nand2tetris-solutions recources verilog
Last synced: 13 Nov 2024
https://github.com/jgroman/fpga-tangprimer25k-experiments
Learning digital design with Tang Primer 25K
Last synced: 19 Nov 2024
https://github.com/jn513/estudos_verilog
Exemplos feito em verilog para estudos
fpga fpga-programming hardware verilog verilog-code verilog-hdl
Last synced: 15 Dec 2024
https://github.com/jamesits/verilog-basic-blocks
数电作业
verilog verilog-components xilinx-ise
Last synced: 05 Dec 2024
https://github.com/rambodrahmani/dalle_porte_and_or_not_al_sistema_calcolatore
Dalle Porte AND OR NOT Al Sistema Calcolatore. Un viaggio nel mondo delle reti logiche in campagnia del linguaggio Verilog.
altera boolean-algebra boolean-logic logic-gates modelsim verilog
Last synced: 29 Dec 2024
https://github.com/ewdlop/verilog-notes
HDLBit-Pratice. https://hdlbits.01xz.net/wiki/Main_Page
combinational-logic finte-state-machine flip-flops sequential-logic verilog
Last synced: 27 Dec 2024
https://github.com/elifgokpinar/microprocessor-design
Quartus Project
microprocessor quartus verilog
Last synced: 13 Nov 2024
https://github.com/yasnakateb/aes
🔐 Hardware Implementation Of AES Algorithm in Verilog HDL
aes aes-128 aes-encryption encryption encryption-algorithm icarus-verilog iverilog verilog verilog-hdl
Last synced: 19 Nov 2024
https://github.com/kaushalmodi/nim-svvpi
Wrapper for SystemVerilog VPI headers sv_vpi_user.h and vpi_user.h
1364-2005 1800-2017 nim pli systemverilog verilog vpi
Last synced: 15 Nov 2024
https://github.com/mssola/hdl
Playing around with Hardware Description Languages.
Last synced: 29 Nov 2024
https://github.com/davidf1000/sistemdigital_vhdl
Final Project for Digital System Lab. Flappy Bird Imitation Game created using VHDL for FPGA DE1.
Last synced: 12 Nov 2024
https://github.com/urish/tt06-spell
A minimal, stack-based programming language created for The Skull CTF
Last synced: 12 Nov 2024
https://github.com/tanmayv25/microprocessor-system-design
Contains the lab work of Microprocessor System Design. All the FPGA prototyping, Drivers and OS modules.
fpga-soc linux-kernel-module sensor-devices verilog xilinx-vivado
Last synced: 30 Dec 2024
https://github.com/adolbyb/vhdl-fpga-nexys-a7
A collection of code from CDA 4240C: Design of Digital System and Lab
artix-7 fpga hardware-description-language hdl nexys-a7 verilog vhdl xilinx-vivado
Last synced: 19 Nov 2024
https://github.com/taffarel55/verilog
Documentação dos exemplos que fiz enquanto estudava a linguagem de descrição de hardware Verilog.
verilog verilog-examples verilog-hdl
Last synced: 09 Jan 2025
https://github.com/cepdnaclk/e18-co502-rv32im-pipeline-implementation-group03
RV32IM Pipeline Processor
Last synced: 12 Nov 2024
https://github.com/cepdnaclk/e18-co502-rv32im-pipeline-implementation-group4
Single-cycle MIPS-like processor with a memory subsystem including a cache.
computer-architecture risc-v verilog
Last synced: 12 Nov 2024
https://github.com/ranitmanik/cs-verilog-assignments
A collection of Verilog code snippets and assignments for computer science coursework.
assignment coding iverilog low-level-programming practice practice-programming verilog
Last synced: 30 Nov 2024
https://github.com/arefin994/bitstreamos
BitStreamOS --- A custom-designed MIPS CPU and operating system built from scratch. Features include a custom instruction set, assembler for converting assembly code to binary, CPU simulation with test benches, waveform visualization, and a basic OS implementation.
asm cpu mips-assembly os verilog
Last synced: 01 Jan 2025
https://github.com/arsham-lh/computer-architecture
Code files related to the Computer Architecture course, taught by M. Movahedin
computer-architecture mips-assembly multi-cycle-processor single-cycle-processor verilog
Last synced: 16 Nov 2024
https://github.com/ilovebacteria/elevator-state-machine
My Digital Logic course project - Elevator state machine
digital-logic moore-machine state-machine verilog
Last synced: 14 Nov 2024
https://github.com/rogerfan48/course-soph1-hdl
Materials and coursework for Hardware Design Lab (Sophomore Fall). Contains exercises, assignments, and laboratory work.
Last synced: 08 Jan 2025
https://github.com/shishir-dey/pcb-dev-fpga-ice40
A 2 layer development board with a Lattice Semiconductor ICE40UP5K-SG48ITR FPGA
development-board fpga hardware pcb-design verilog
Last synced: 14 Nov 2024
https://github.com/mohammadmahdi-abdolhosseini/computer-architecture-lab
Computer Architecture Lab - Assignments - Fall 2023
arm-processor fpga modelsim quartus2 systemverilog verilog vhdl
Last synced: 07 Jan 2025
https://github.com/mcleber/verilog_half_adder
Verilog half adder
half-adder verilog verilog-hdl
Last synced: 13 Nov 2024
https://github.com/davoodeh/verilog2hspice
Do some simple conversions on Verilog files to make them compatible with HSpice
Last synced: 15 Dec 2024
https://github.com/grachale/microarchitecture_risc-v_isa
Design of a Processor Microarchitecture Supporting a Chosen Subset of RISC-V ISA Instructions.
assembly isa microarchitecture risc-v verilog
Last synced: 13 Nov 2024
https://github.com/yvesemmanuel/introduction_verilog
digital systems
digital-systems verilog verilog-components verilog-project
Last synced: 16 Nov 2024
https://github.com/yvesemmanuel/microwave
second project - Digital System
digital-systems verilog verilog-components verilog-project
Last synced: 16 Nov 2024
https://github.com/youseftareq33/digital_buildcombinationalcircuit_2
Using Verilog HDL on Quartus application build combinational circuit
Last synced: 24 Dec 2024
https://github.com/jjateen/snake-game-verilog
This repository showcases a Verilog-based Snake and Apple Game, developed for the ECL 106: Digital System Design with HDL course. Running on an Altera DE10-Lite FPGA board and displayed on a VGA monitor, players control a snake to collect apples while avoiding obstacles. The snake grows longer with each apple, making the game progressively harder.
altera-fpga de10-lite fpga quartus-prime verilog verilog-project
Last synced: 16 Nov 2024
https://github.com/coldnew/nand2tetris
My notes and impement on Nand2Tetris courses
coursearea nand2tetris personal-notes verilator verilog
Last synced: 15 Nov 2024
https://github.com/daulpavid/verilog_template
Boilerplate project template for verilog that includes directories for simulation, documentation, and formal verification.
cmake verilator verilog verilog-template
Last synced: 15 Nov 2024
https://github.com/karagultm/datapath
The project involved extending the processor to support six new instructions: brv, jmxor, nori, blezal, jalpc, and baln. This required modifications to the control logic, the addition of new multiplexers, and the inclusion of status register flags to handle the specific behaviors of these instructions.
mips mips-architecture mips-assembly verilog
Last synced: 24 Dec 2024
https://github.com/rejunity/atari-2600-fpga
Continue development of Atari 2600 in Verilog. Based on the original work by Daniel Beer.
atari-2600 atari2600 fpga retrogaming verilog
Last synced: 24 Nov 2024
https://github.com/mongshil553/digital-engineering-verilog-assignments
Sophomore 2021 1st Semester Digital Engineering Verilog Assignments
fpga-programming verilog xilinx-vivado
Last synced: 14 Nov 2024
https://github.com/kayejd/nexysa7-fpga-programming
Embedded Programming Projects
embedded-systems fpga-programming verilog vivado
Last synced: 17 Nov 2024
https://github.com/kayejd/hvac-system
School Related Project
capstone digital digital-signal-processing engineering-design verilog
Last synced: 17 Nov 2024
