Ecosyste.ms: Awesome
An open API service indexing awesome lists of open source software.
Verilog
Verilog is a widely-used hardware description language (HDL) that enables designers to model, simulate, and synthesize digital circuits. It provides a text-based format for specifying the structure and behavior of electronic systems, making it easier to design complex hardware components such as microprocessors, memory, and communication devices.
- GitHub: https://github.com/topics/verilog
- Wikipedia: https://en.wikipedia.org/wiki/Verilog
- Aliases: hdl, hardware-description-language,
- Last updated: 2025-01-09 00:31:35 UTC
- JSON Representation
https://github.com/dvvcz/viva
Experimental cli to create HDL projects using Vivado, outside of their IDE.
cli hardware hdl package-manager rust systemverilog verilog vivado
Last synced: 05 Jan 2025
https://github.com/teddy-van-jerry/sdr-psk-fpga
Dual-Mode PSK Transceiver on SDR With FPGA
amd bpsk costas-loop demodulation fpga gardner modulation psk qpsk sdr software-defined-radio synchronization transceiver verilog vivado xilinx zynq zynq-7000 zynq-7020
Last synced: 03 Dec 2024
https://github.com/yugr/parmatch
A simple script for finding unbound parameters in Verilog module instantiations.
static-analysis static-analyzer verilog
Last synced: 27 Dec 2024
https://github.com/cw1997/graphical_card
a graphical card for displaying text on VGA text mode by D-Sub port
graphical-programming hardware hardware-designs systemverilog-simulation verilog verilog-project
Last synced: 28 Nov 2024
https://github.com/kaushalmodi/nim-systemverilog-vpi
Using Nim to interface with Verilog and SystemVerilog test benches via VPI
1364-2005 1800-2017 c cpp nim pli systemverilog verilog vpi
Last synced: 15 Nov 2024
https://github.com/akhilrai28/single-port-ram
This project implements a single-port RAM using Verilog. The design simulates a memory module with a single read/write port, supporting basic memory operations like data storage and retrieval. It includes testbenches for functional verification and timing analysis to ensure reliable operation.
digital-circuits fpga fpga-programming hardware hardware-description-language memory-design ram single-port synchronous testbench verilog
Last synced: 15 Dec 2024
https://github.com/cepdnaclk/e16-co502-rv32im-pipeline-implementation-group1
The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pipeline CPU supports the entire RV32IM ISA which contains 45 instructions. The designed pipeline CPU was implemented using behavioral modeling in verilogHDL and icarus Verilog was used compile and simulate. gtkWave was used to observe the behavior.
computer-architecture pipeline risc-v rv32im verilog
Last synced: 12 Nov 2024
https://github.com/amirhnajafiz-university/s3lc02
Logical circuits course final project.
circuit internet-of-things logical-circuits verilog
Last synced: 26 Dec 2024
https://github.com/akhilrai28/gravity-accelerator
This project implements a gravity accelerator using Verilog and Vivado. It simulates the physics of gravitational acceleration, calculating velocity and position over time within a digital circuit environment. The project includes testbenches and waveform analysis to ensure accurate simulation and performance.
digital-simulation fpga gravity-algorithm gravity-model gravity-simulation hardware hardware-acceleration hardware-designs physics-simulation testbench verilog vivado
Last synced: 15 Dec 2024
https://github.com/gergoerdi/clash-bounce-bench
Benchmark for various methods of simulating Clash
benchmark c clash haskell sdl2 simulation verilator verilog
Last synced: 16 Nov 2024
https://github.com/algosup/2024-2025-project-1-fpga-team-7
This version of the "Frogger" game is made using a "go-board" and the "verilog" programming language. It takes only the road part of the original game and is made to be used with a vga screen.
frogger frogger-game go-board-game verilog
Last synced: 16 Nov 2024
https://github.com/donn/swiftlog
An IcarusVerilog VPI bridge for the Swift Programming Language.
Last synced: 28 Nov 2024
https://github.com/raleighlittles/basys3countdownclock
Extremely basic countdown clock project for the Basys 3 FPGA development board.
basys-3 basys3 fpga hdl seven-segment-display verilog vivado xdc xilinx
Last synced: 28 Nov 2024
https://github.com/gogolb/ee175
EE 175 Senior Design. Multibaseline Stereo Camera
computer-vision matlab ov7670 senior-design slam stereo-vision university-course university-project verilog vivado xilinx zynq
Last synced: 01 Dec 2024
https://github.com/muhammadtalhasami/rv32i_single_cycle
This repository contains an implementation of a RV32I fetch pipeline microprocessor. The RV32I is a 32-bit RISC-V instruction set architecture, with the 'I' extension indicating the base integer instructions.
fetch-stage-pipeline gtkwave hardware-designs muhammadtalhasami-github- pipeline-processor risc-v-assembly risc-v-pipeline risc-v-processor risc-v-processor-images rv32i rv32i-processor single-cycle-processor single-cycle-processor-gtkwave-image system-verilog system-verilog-codes verilator verilog verilog-code-examples verilog-codes vhdl
Last synced: 25 Dec 2024
https://github.com/jn513/grande-risco-5
Processador RISC-V multi ciclo com implementação RV32I construído em alguns dias de folga.
arquitetura fpga risc-v riscv riscv32 verilog verilog-hdl
Last synced: 15 Dec 2024
https://github.com/zannatul-naim/digital-system-design
Digital System Design Lab Codes using Verilog
adder d-flipflop flipflop full-adder half-adder jk-flipflop ripple-carry-adder t-flipflop verilog
Last synced: 26 Dec 2024
https://github.com/jn513/pequeno-risco-5
Processador RISC-V de ciclo único com implementação RV32I construído em alguns dias de folga.
arquitetura risc-v riscv riscv32 verilog verilog-hdl
Last synced: 15 Dec 2024
https://github.com/pvgupta24/cse-labs
Dump for CSE Lab assignments and programs
algorithms c computer-architecture cpp data-structures mips opengl verilog
Last synced: 06 Jan 2025
https://github.com/ain1084/audio_echo_effect
Simple echo effect implementation with digital audio processing.
audio-processing i2s-audio lattice-fpga verilog
Last synced: 20 Dec 2024
https://github.com/samridhisainii/digitaldesign
These are the question of digital design lab from our subject digital design lab which were done in lab
Last synced: 29 Nov 2024
https://github.com/bugenzhao/mips
👨🏻💻 Pipelined MIPS I CPU with 49 instructions & multiplication & direct-mapped cache in Verilog.
Last synced: 23 Nov 2024
https://github.com/gyeonghokim/riscv_core
building 32bit risc-v core and Machine Learning for Branch Prediction
Last synced: 29 Dec 2024
https://github.com/liu42/processor
《计算机组成原理》课程设计，基于 MIPS 的流水线 CPU 系统设计。
architecture computer-architecture course-project cpu fpga homework-project mips mips-architecture mips-processor pipeline verilog
Last synced: 21 Dec 2024
https://github.com/aben20807/computer_organization
1052_計算機組織 COMPUTER ORGANIZATION
cache cpu datapath pipeline single-cycle verilog
Last synced: 16 Nov 2024
https://github.com/risto97/cascade_classifier
Python, C, RTL implementation of Viola Jones cascade classifier, using pretrained model from opencv.
face-detection fpga object-detection pygears python verilog viola-jones
Last synced: 21 Dec 2024
https://github.com/hywooo/docker-bsv-wsl2
🐋Docker for Bluespec SystemVerilog (BSV) on WSL2, compatible with WangXuan95/BSV_Tutorial_cn. 适用于BSV中文教程的Docker BSV （WSL2）环境。
bluespec-systemverilog bsv docker dockerfile packages systemverilog verilog vivado
Last synced: 29 Oct 2024
https://github.com/eomielan/16-bit-risc-machine
16-bit CPU architecture implementation and verification using SystemVerilog
cpu-architecture systemverilog verilog
Last synced: 30 Dec 2024
https://github.com/muhammadtalhasami/sv_verilator
System verilog learning journey. Here in this repo you learn about how to write system verilog test bench using verilator tool a c++ test bench. Verilator is basically a 2 state tool .
system-verilog-testbench systemverilog testbench verification verilator- verilator-testbench verilog verilog-hdl
Last synced: 06 Nov 2024
https://github.com/algosup/2024-2025-project-1-fpga-team-4
Recreating the arcade game Frogger using FPGA and Verilog
fpga retrogaming school-project verilog
Last synced: 16 Nov 2024
https://github.com/akhilrai28/alarm-clock
This project implements a fully functional digital alarm clock using Verilog and Vivado. The design includes features such as setting the time, alarm functionality, and real-time clock display. The project simulates clock timing and alarm triggers, with testbenches for verifying accuracy and reliability on FPGA.
alarm alarm-clock clock fpga hardware real-time simulation testbench verilog vivado
Last synced: 15 Dec 2024
https://github.com/ashkan-khd/conways-game-of-life-verilog
An easy approach for Conway's Game Of Life with Verilog HDL
conways-game-of-life conways-game-of-life-verilog game-of-life game-of-life-verilog testbench verilog verilog-game-of-life verilog-hdl
Last synced: 20 Dec 2024
https://github.com/ehsanshahbazii/digital-vlsi-system-design-projects
سورس کد پروژه های درس طراحی سیستم های دیجیتال برنامه پذیر دانشگاه تبریز مقطع کارشناسی رشته مهندسی کامپیوتر
verilog verilog-code verilog-components verilog-project vlsi
Last synced: 10 Nov 2024
https://github.com/lebrancconvas/verilog-playground
Verilog Playground.
digital-electronics logic-gates verilog
Last synced: 08 Jan 2025
https://github.com/meetps/ee-214
VHDL and Verilog Codes for Digital Lab.
digital-logic fpga verilog vhdl
Last synced: 04 Jan 2025
https://github.com/pconst/xilinx_max_power
Creating dummy load to dissipate maximum power in Xilinx FPGA
arty board cooling development digilent fpga power shift-register soc systemverilog test ultrascale verilog xilinx zinq
Last synced: 12 Nov 2024
https://github.com/urish/tt05-silife-8x8
Game of Life in Silicon (8x8)
game-of-life tiny-tapeout verilog
Last synced: 12 Nov 2024
https://github.com/byte-me404/jku-tt06-ps2-morse-encoder
Custom ASIC design which decodes a PS/2 keyboard, furthermore it encodes and outputs the data as morse code
asic ps2-keyboard tinytapeout verilog
Last synced: 05 Jan 2025
https://github.com/yasnakateb/pipelinedmips
🔮 A 16-bit MIPS Processor Implementation in Verilog HDL
cpu icarus-verilog iverilog mips mips-pipeline mips-processor pipeline verilog verilog-hdl
Last synced: 19 Nov 2024
https://github.com/sinakarvandi/hardware-design-stack
The source codes used in the blog post available at: https://rayanfam.com/topics/hardware-design-stack/
asic asic-design chisel chisel3 fpga gtkwave modelsim netlist openlane openram verilator verilog vhdl vitis vitis-hls vivado vivado-hls
Last synced: 17 Nov 2024
https://github.com/kyori19/verilog-otp
VerilogHDL implementation of One-Time Password Algorithm (HOTP)
hotp onetimepassword systemverilog verilog verilog-hdl
Last synced: 17 Nov 2024
https://github.com/engineeringsoftware/hdlp
Code and data for "On the Naturalness of Hardware Descriptions" in ESEC/FSE'20
deep-learning hardware-description-language machine-learning naturalness pytorch systemverilog verilog vhdl
Last synced: 18 Nov 2024
https://github.com/z4yx/thinpad-controller-zynq
RTL project for the controller SoC on Thinpad
Last synced: 01 Dec 2024
https://github.com/yahia3200/spi-protocol-implementation-using-verilog
Implementing SPI interface using Verilog
Last synced: 21 Nov 2024
https://github.com/phillbush/tbgen
Testbench generator in AWK for Verilog modules
awk testbench testbench-generator testbench-generator-verilog verilog
Last synced: 22 Nov 2024
https://github.com/alokmenghrajani/adventofcode2018
Advent of Code 2018. Solutions using Verilog + icestick fpga! ☃️🎄🎁🦌🎅
2018 advent-of-code-2018 advent-of-code-2018-fpga adventofcode adventofcode2018 fpga solutions upping-the-ante verilog
Last synced: 25 Nov 2024
https://github.com/kigawas/mipscpu
A single cycle CPU running on Xilinx Spartan 6 XC6LX16-CS324, supporting 31 MIPS instructions.
educational-project mips verilog
Last synced: 12 Nov 2024
https://github.com/cpehle/cascade
Cycle based C++ hardware simulation infrastructure
Last synced: 15 Dec 2024
https://github.com/barrettotte/subarashii-cpu
A 16-bit RISC CPU inspired by MIPS. I designed this to learn more about computer architecture/organization.
cpu homebrew risc-processor verilog verilog-cpu
Last synced: 09 Dec 2024
https://github.com/shyamal-anadkat/the-11-of-us
adc ece551 flight-controller hdl integrator quadcopter synthesis system-verilog uart verilog vhdl
Last synced: 16 Dec 2024
https://github.com/pirate-emperor/cipherx
CipherX is a verification project for Advanced Encryption Standard (AES-128) using Universal Verification Methodology (UVM). It leverages Verilog, SystemVerilog, and Python to ensure robust encryption algorithm validation, integrating comprehensive UVM components and tests.
aes-128 cryptography cryptography-algorithms dataencryption dataencryptionstandards digitaldesign encrytption hardwareverification python security testing-framework uvm verification verilog
Last synced: 04 Dec 2024
https://github.com/viktor-prutyanov/fpga-ir
IR receiver with UART interface
fpga ir-receiver remote-control verilog
Last synced: 12 Dec 2024
https://github.com/bryanlimy/flappybird-verilog
Flappy-Bird-liked game in Verilog
flappy-bird flappy-bird-game verilog
Last synced: 17 Dec 2024
https://github.com/alyssonmach/logic-circuits
Simulations made in the UFCG logic circuit laboratory.
laboratory logic-circuit logisim quartus ufcg verilog
Last synced: 24 Dec 2024
https://github.com/amirreza81/digital-systems-design
Digital Systems Design - Spring 2023 - Sharif University of Technology
assembly digital-system-design verilog
Last synced: 05 Jan 2025
https://github.com/yugr/gatecheck
Yet another Verilog static analyzer
clock-g gating static-analysis static-analyzer verilog
Last synced: 27 Dec 2024
https://github.com/dineshpinto/stm32f4
Combining an FPGA, micro-controller and AWG for nanosecond photon counting
assembly awg c microcontroller photonics verilog
Last synced: 09 Dec 2024
https://github.com/sgq995/rc4-de0-nano-soc
It's a cryptoprocessor that implements de RC4 algorithm
de0-nano-soc fpga fpga-soc rc4 verilog
Last synced: 07 Jan 2025
https://github.com/lorhansohaky/ufscar
Arquivos de atividades da UFSCar
arquitetura-de-computadores banco-de-dados c cap cgi compilador compiladores computacao-grafica cpp dc estruturas-de-dados grafos ori orientacao-a-objetos paa paradigmas sistemas-operacionais ufscar verilog
Last synced: 05 Dec 2024
https://github.com/rauhul/ece385
Digital Systems Laboratory UIUC FA 2016
altera fpga quartus-prime systemverilog verilog
Last synced: 02 Dec 2024
https://github.com/jamesits/verilog-basic-blocks
数电作业
verilog verilog-components xilinx-ise
Last synced: 05 Dec 2024
https://github.com/bilalm04/combination-lock-fsm
Moore FSM combination lock in Verilog for DE1-SOC Board.
Last synced: 31 Dec 2024
https://github.com/zazi2002/computer-architectur-lab
Computer Architecture Lab projects with various fundamental concepts, including multi-cycle MIPS processors and PIC32 microcontroller programming.
counter mips multicycle-processor pic32 verilog
Last synced: 28 Dec 2024
https://github.com/polaris000/cs_f342
Lab assignments and some practise done for the Computer Architecture course at BITS Pilani
assembly bits-pilani comparch computer-architecture labs practise verilog
Last synced: 11 Nov 2024
https://github.com/andrejchoo/uart_spiflash_programmer_on_fpga
UART programmer SPI FLASH 25-series on FPGA or CPLD
fpga programmer spi-flash verilog
Last synced: 11 Dec 2024
https://github.com/amir78729/logical-circuits-course-final-project
My Logical Circuits course Final Project - Fall98(2019) - VERILOG
Last synced: 17 Nov 2024
https://github.com/tomarus/midirouter
CMOD-A7 FPGA MIDI Merger/Router/Switch.
Last synced: 15 Dec 2024
https://github.com/m13253/sbmips
Naïve MIPS32-like CPU design with pipeline on a Xilinx FPGA
Last synced: 05 Dec 2024
https://github.com/marceldobehere/goofy-cpu-verilog
cpu cpu-simulator goofy goofy-cpu sim verilog
Last synced: 04 Jan 2025
https://github.com/hugech38/mips
🐢 用 Verilog 实现的单周期 MIPS 指令集的 CPU，并用它来计算斐波那契数。
cpu mips mips-architecture mips-instructions mips-processor verilog vhdl
Last synced: 20 Nov 2024
https://github.com/yaxsomo/iris_cubesat
This Repository is dedicated to FPGA development of the IRIS CubeSat
aerospace cubesat fpga free-space-optical-communiucation satellite verilog vhdl vivado xilinx
Last synced: 12 Nov 2024
https://github.com/brlin-tw/clean-filter-for-verilog
Clean your Verilog design code!
bash clean-filter filter git git-attributes istyle vdent verilog
Last synced: 21 Nov 2024
https://github.com/sauravmaheshkar/verilog-template
❄️ Template for Verilog Projects using iverilog and gtkwave (nix devShell supported)
hardware-description-language template-project verilog verilog-template vhdl
Last synced: 06 Dec 2024
https://github.com/abtinz/logic-circuits-final-project
Aut Logic Circuits Finall Project Fall 1400
Last synced: 12 Nov 2024
https://github.com/abdallahabusedo/cmp305-introduction-verilog
introduction to Verilog in Integrated Circuit Design And VLSI technology
verilog verilog-code verilog-hdl verilog-project
Last synced: 13 Dec 2024
https://github.com/harshalmittal4/24-bit-risc-processor
Computer Architecture-MIPS Processor simulation in verilog with self developed ISA
Last synced: 19 Nov 2024
https://github.com/valaphee/redsynth
Generate redstone circuits out of Verilog.
bukkit-plugin fpga minecraft redstone synthesis verilog
Last synced: 07 Jan 2025
https://github.com/rambodrahmani/dalle_porte_and_or_not_al_sistema_calcolatore
Dalle Porte AND OR NOT Al Sistema Calcolatore. Un viaggio nel mondo delle reti logiche in campagnia del linguaggio Verilog.
altera boolean-algebra boolean-logic logic-gates modelsim verilog
Last synced: 29 Dec 2024
https://github.com/jgroman/fpga-tangprimer25k-experiments
Learning digital design with Tang Primer 25K
Last synced: 19 Nov 2024
https://github.com/junzhengca/space-enemies
Rip off of space invaders coded in Verilog with VGA output support, intended for DE2-115 FPGA board. Final project for CSCB58.
assignment de2-115 hardware project verilog
Last synced: 13 Dec 2024
https://github.com/liu42/pipeline
《计算机组成原理》课程设计，基于 MIPS 系统的流水线 CPU 设计
architecture computer-architecture course-project cpu fpga homework-project mips mips-architecture mips-processor pipeline verilog
Last synced: 23 Nov 2024
https://github.com/ain1084/dual_clock_buffer
Dual clock buffer for modules connected by valid-ready protocol
Last synced: 20 Dec 2024
https://github.com/kar-dim/icsd-digitalsystems
Some Verilog projects, implemented as part of my university coursework (2013-2019, Information and Communications Systems Engineering, University of the Aegean).
Last synced: 04 Jan 2025
https://github.com/weisrc/fpgaudio
MIDI file to Verilog Code Generation - FPGAudio!
Last synced: 23 Dec 2024
