https://github.com/ellisgl/sap-1-v2-mojo

SAP-1 CPU in Verilog for the Mojo FPGA board - has seperate address bus.

cpu fpga mojo-fpga-board verilog

Last synced: 18 Nov 2024

https://github.com/delhatch/red_tracker

Uses the D8M camera module, then processes the image to detect red objects, and then overlay an x,y crosshair on the largest red object. See the video. Pure Verilog. (No soft-core processor.)

altera de2-115 fpga image-processing verilog vga vga-controller

Last synced: 13 Nov 2024

https://github.com/catkira/cic

HDL code for a complex multiplier with AXI stream interface

axis hdl verilog

Last synced: 01 Nov 2024

https://github.com/chipsalliance/f4pga-v2x

Tool for converting specialized annotated Verilog models into XML needed for Verilog to Routing flow.

f4pga python v2x verilog xml

Last synced: 05 Nov 2024

https://github.com/lc044/cpu

五级流水线CPU设计

cpu verilog

Last synced: 22 Nov 2024

https://github.com/jasonbrave/pci-edu

SystemVerilog implemention of QEMU PCI edu device

pci pci-bus pci-devices systemverilog verilator verilog

Last synced: 20 Dec 2024

https://github.com/mattvenn/frequency_counter

Project 2.2 Frequency counter

asic hdl verilog

Last synced: 15 Dec 2024

https://github.com/pescetti-studio/flipga01

FPGA (Verilog) implementation of the Flip01 8-bit processor.

8-bit 8-bit-computer 8-bit-cpu 8bit cpu flip01 fpga verilog verilog-project

Last synced: 21 Nov 2024

https://github.com/mikeroyal/fpga-guide

FPGA Guide

fpga fpga-board fpga-programming fpga-soc hardware verilog

Last synced: 12 Dec 2024

https://github.com/ben-marshall/microcoder

Define custom assembly-like instructions and use them to write programs which are transpiled into synthesisable Verilog code.

assembly microcode microcontroller synthesis verilog

Last synced: 29 Nov 2024

https://github.com/circuitvalley/wireframe-fpga

Source files Related to WireFrame FPGA Board published on www.circuitvalley.com

diy fpga verilog xilinx

Last synced: 28 Dec 2024

https://github.com/obijuan/monsterled

VGA controller for Open FPGAs. Convert your VGA screen into a big LED :-)

fpga fpgawars hardware icestorm icestudio icezum open-fpgas verilog vga-controller

Last synced: 24 Dec 2024

https://github.com/hukenovs/blackman_harris_win

Blackman-Harris Window functions (3-, 5-, 7-term etc.) from 1K to 64M points based only on LUTs and DSP48s FPGA resources. Main core - CORDIC like as DDS (sine / cosine generator)

cordic cordic-algorithm cosine dds digital-signal-processing dsp fpga hamming-window hann-window impulse-response kaiser-window matlab octave sine spectral-analysis taylor-method taylor-series verilog vhdl window-function

Last synced: 19 Nov 2024

https://github.com/itzzinfinity/100-days-of-rtl

Trying to get a new skill

altera digital electronics gowin modelsim quartus-prime rtl testbench verilog vivado xilinx xilinx-vivado

Last synced: 26 Dec 2024

https://github.com/obijuan/ctif-madrid-2018-fpgas-libres

Material del curso de DISEÑO DE SISTEMAS DIGITALES EN VERILOG USANDO FPGAS LIBRES. Centro: CTIF Madrid-capital, 2018

course-materials curso fpga icestorm icestudio icezumalhambra openfpga verilog

Last synced: 24 Dec 2024

https://github.com/harbaum/pacman-tangnano9k

A Pac-Man Arcade implementation for the TangNano9K using HDMI

arcade fpga gowin hdmi pacman tangnano9k verilog

Last synced: 15 Nov 2024

https://github.com/harbaum/ikbd

Verilog implementation of the Atari ST IKBD

atari-st atari-st-ikbd fpga ikbd mist verilog

Last synced: 15 Nov 2024

https://github.com/raleighlittles/applied_digital_logic_exercises_using_fpgas

Selected projects from "Applied Digital Logic Exercises using FPGAs", by Kurt Wick.

applied-digital-logic-exercises artix-7 basys3 fpga hdl microblaze-mcs verilog vivado

Last synced: 28 Nov 2024

https://github.com/lsc-unicamp/processor-ci-controller

Controller module for RISC-V core CI/CD

fpga riscv verilog

Last synced: 13 Nov 2024

https://github.com/anupam-io/es203-coa-cnn

ES-203 Computer Organization & Architecture CNN on FPGA board

cnn cnn-classification cnn-keras cnn-model fpga fpga-programming machine-learning machinelearning verilog vivado

Last synced: 16 Dec 2024

https://github.com/jotego/jt5205

Verilog ADPCM decoder compatible with OKI MSM5205

adpcm fpga verilog

Last synced: 15 Oct 2024

https://github.com/enkerewpo/methane

A polyphonic synthesizer built on fpga and esp32

chisel3 esp32 fpga music-hardware synthesizer systemverilog verilog

Last synced: 11 Nov 2024

https://github.com/emsec/hal-benchmarks

Benchmark suite for HAL

hardware netlist reverse-engineering verilog vhdl

Last synced: 12 Nov 2024

https://github.com/way-zer/fpga

My Project about FPGA, 包含数电课内作业 和 数电实验 彩蛋机

experiment fpga verilog

Last synced: 14 Nov 2024

https://github.com/wpmed92/riscyd2

A RISC-V based microcontroller

cpu hardware microcontroller python riscv verilog

Last synced: 09 Dec 2024

https://github.com/dawsonjon/chips_v

RISC-V System on Chip Builder

c chip-builder chips embedded fpga fpga-soc python risc-v riscv soc verilog

Last synced: 01 Dec 2024

https://github.com/donn/phi

Hardware description language that tries not to suck

compilers eda fpga hdl phi systemverilog verilog

Last synced: 28 Nov 2024

https://github.com/delhatch/zedboard_mandel

Mandelbrot generator on the Zedboard. The image is output on the VGA port. Pure Verilog RTL, no ARM core.

verilog zedboard

Last synced: 13 Nov 2024

https://github.com/vegaluisjose/aws-fpga-notes

Amazon F1 instance walk through tutorial

afi aws-fpga fpga tutorial verilog

Last synced: 06 Dec 2024

https://github.com/kevinzakka/vector-norm-processor

Verilog Implementation of a Vector L2 Norm Processor

controller datapath processor vector-norm verilog

Last synced: 16 Dec 2024

https://github.com/danielvieiravega/vcdparser

Value Change Dump (VCD) File

hdl simulations value-change-dump vcd verilog vhdl

Last synced: 15 Nov 2024

https://github.com/catkira/complex_multiplier

HDL code for a complex multiplier with AXI stream Interface

axis fpga hdl verilog

Last synced: 01 Nov 2024

https://github.com/hukenovs/fp32_logic

Floating point FP32 core HDL. For Xilinx FPGAs. Include base converters and some math functions.

altera digital-signal-processing dsp floating-point fpga ieee-754 ieee754 integer-arithmetic verilog vhdl xilinx

Last synced: 19 Nov 2024

https://github.com/aekanshd/booths-multiplier-using-verilog

booths-algorithm verilog verilog-project

Last synced: 15 Nov 2024

https://github.com/porglezomp/nangate

Yosys passes to syntheize to NaN gates (à la http://tom7.org/nand/)

logic-synthesis nan-gate verilog yosys yosys-plugin

Last synced: 27 Oct 2024

https://github.com/ahmedsobhy01/aes-verilog

An implementation of the Advanced Encryption Standard (AES) encryption algorithm using Verilog supporting AES-128, AES-192, and AES-256 encryption/decryption

aes aes-128 aes-192 aes-256 altera decryption encryption fpga verilog

Last synced: 27 Dec 2024

https://github.com/addisonelliott/logifindfpgatest

This is a Quartus Prime FPGA project testing the functionality of the LogiFind Altera Cyclone IV EP4CE6E22C8N Development Board. This product can also be found on eBay where I bought it from. I hope to provide base code that will help others in their learning with this development board.

7-segment altera buzzer cyclone-iv easyfpga ep4ce6e22c8n fpga ir-receiver logifind nec-verilog pl2303 quartus-prime uart-verilog verilog verilog-hdl

Last synced: 08 Dec 2024

https://github.com/doctorwkt/verilog_tic-tac-toe

An implementation of "Tic Tac Toe" in Verilog. FPGA versus user, FPGA knows how to win!

fpga game verilog

Last synced: 27 Dec 2024

https://github.com/mattco98/legv8-processor

A Verilog implementation of a LEGv8 Processor

armv8 computer-arch legv8 processor verilog

Last synced: 20 Dec 2024

https://github.com/catkira/dds

HDL code for a DDS (direct digital synthesizer) with AXI stream interface

dds fpga hdl verilog

Last synced: 01 Nov 2024

https://github.com/styczynski/fpga-verilog

Collection of my projects that was made as a part of Warsaw University FPGA course

fpga fpga-board fpga-programming hardware uart verilog vga

Last synced: 15 Nov 2024

https://github.com/wannabeog/csn-221-project

Implementation of a 24 bit RISC processor

pipeline-processor risc-processor verilog

Last synced: 05 Jan 2025

https://github.com/racerxdl/fpga-serial-hello

FPGA Verilog Serial Hello World + Led Blink

arduino fpga hello-world lattice led-blink verilog yosis

Last synced: 07 Nov 2024

https://github.com/malaksadek/statictiminganalyzer

A Logic Circuit Static Timing Analyzer Implemented in Python 🔌 ⚡ (2018)

c graph-algorithms html json logic-circuit logic-gates python scl static-timing-analysis verilog verilog-hdl

Last synced: 17 Nov 2024

https://github.com/HEP-SoC/SoCMake

CMake based hardware build system

asic build-automation build-system cmake fpga integrated-circuits system-on-chip systemverilog verilator verilog vhdl vhdl-language

Last synced: 27 Nov 2024

https://github.com/teddy-van-jerry/arm_lite

A lite version of ARM CPU that extends ARM LEGv8

arm armv8 cpu forwarding pipeline verilog verilog-hdl

Last synced: 03 Dec 2024

https://github.com/delhatch/pure_mandel

FPGA paramatized mandelbrot generator. I have tested instantiating 4, 8, and 12 calculating engines. It has a built-in VGA controller (at 640x480) with internal dual-port RAM as the frame buffer. With 4 engines it runs at 100 MHz (5 frames/sec). With 12 engines, at 112 MHz, it hits 20.5 frames/sec.

altera de2-115 fpga mandel mandelbrot verilog vga vga-controller

Last synced: 13 Nov 2024

https://github.com/ben-marshall/verilog-probe

A very small and simple debug probe designed to be very easy to interface with and be usable via SPI, JTAG and UART.

debugger fpga hdl probe python3 uart verilog

Last synced: 29 Nov 2024

https://github.com/rismicrodevices/rmr8pm3001a

Taurus 3001 RISC-V 64-bit Privileged Minimal System Processor for T110/T28 ASIC

jasse out-of-order risc-v rv64 rv64i verilator verilog verilog-project ysyx3 ysyx4

Last synced: 16 Nov 2024

https://github.com/heartacker/mynotes

git latex markdown verilog vscode

Last synced: 08 Nov 2024

https://github.com/weisrc/web-verilog-poc

Running verilog on hardware, desktop and the web

emscripten fpga poc systemverilog verilator verilog wasm webassembly

Last synced: 10 Oct 2024

https://github.com/davidbrochart/pyclk

Python implementation of a Hardware Description Language (HDL)

fpga hdl myhdl python verilog vhdl

Last synced: 11 Oct 2024

https://github.com/hdl-util/clock-domain-crossing

Utilities for clock-domain crossing with an FPGA

clock-domain-crossing clock-domains clock-synchronization fpga systemverilog verilog

Last synced: 15 Nov 2024

https://github.com/aofarmakis/nibbling-bits

Design and documentation for a very simple 4-bit processor named NibbleBuddy and its assembler.

assembler assembly hardware-description-language processor-design verilog

Last synced: 07 Dec 2024

https://github.com/takenobu-hs/stg-verilog

STG Physical Machine with Verilog-HDL for Haskell(GHC)

haskell verilog

Last synced: 07 Nov 2024

https://github.com/frenzyexists/computer-architecture-project-sparc

Final Project of the Computer Architecture (ICOM4215) course, Spring 2023. The project documents the journey of three students learning the basics of the vast world of FPGAs and hardware design in general. Here We designed a SPARC-Based Processor in Verilog :D

computer-architecture forwarding-unit fpga hardware icom-4215 instruction-semantics sparc-architecture sparcv8 uprm verilog

Last synced: 03 Jan 2025

https://github.com/comradeprogrammer/verilog_mips_cpu_buaa

BUAA Computer_Organizations Projects

buaa buaa-co mips32cpu scse verilog

Last synced: 16 Dec 2024

https://github.com/hazooree/lenet-cnn-accelerator-hardware-for-fpga

An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017

acceleration cnn cnns fpga handwritten-digit-recognition lenet verilog

Last synced: 10 Nov 2024

https://github.com/yasnakateb/pipelinedarm

💎 A 32-bit ARM Processor Implementation in Verilog HDL

arm arm-pipeline arm-processor cpu icarus-verilog iverilog verilog verilog-hdl

Last synced: 19 Nov 2024

https://github.com/amirhnajafiz-university/s3lc01

Basic collection for learning logic circuits.

logic-circuit verilog

Last synced: 26 Dec 2024

https://github.com/yasnakateb/nocrouter

👶🏻 My first baby steps into the world of NoC

icarus-verilog iverilog router verilog verilog-hdl

Last synced: 19 Nov 2024

https://github.com/arkaeriit/reflet

A processor with a custom ISA

assmbler processor soft-processor verilog

Last synced: 29 Nov 2024

https://github.com/mrlsd/fpga

Research & Development FPGA projects for different boards

altera-fpga fpga sipeed-tang-nano-9k systemverilog verilog

Last synced: 06 Jan 2025

https://github.com/geekalexis/superscalar-mips

A MIPS CPU with dual-issue, out-of-order, and 5-stage pipelines

mips processor-architecture verilog

Last synced: 13 Nov 2024

https://github.com/izyasoft/easyhdllib

A coocbook of HDL (primarily Verilog) modules

altera clock-divider fifo fpga frequencies frequency-analysis hdl verilog verilog-components verilog-hdl verilog-library verilog-snippets xilinx-fpga

Last synced: 20 Dec 2024

https://github.com/algosup/2024-2025-project-1-fpga-team-5

1st project of the year 2024-2025, recreate Frogger in FPGA / verilog

fpga retrogaming school-project verilog

Last synced: 16 Nov 2024

https://github.com/programmerjake/rv32

RISC-V 32-bit processor that runs a 2.5D maze game; Built for CPTR380 Winter of 2018 at Walla Walla University

fpga maze-game raycasting risc-v verilog

Last synced: 11 Nov 2024

https://github.com/delhatch/iir_eq

IIR audio filter in Verilog, running on Zedboard. Fractional integer coefficients.

equalizer iir iir-filter iir-filters verilog zedboard

Last synced: 13 Nov 2024

https://github.com/algosup/2024-2025-project-1-fpga-team-6

This project aims to create a Frogger game using the FPGA (Field Programmable Gate Array) technology and Verilog.

console controller fpga frogger-game game-development lilypad verilog

Last synced: 16 Nov 2024

https://github.com/mattvenn/seven_segment_seconds

Demo project for Zero to ASIC course & presentations

asic demo verilog

Last synced: 15 Dec 2024

https://github.com/markmll/tang_nano_as_shipped

A close approximation of the demo code on Sipeed Tang Nano boards as shipped.

fpga verilog vhdl

Last synced: 21 Dec 2024

https://github.com/jeffdecola/control-fpga-via-raspi-and-webserver

Control a FPGA via a Raspberry Pi and a Webserver.

arty-s7 fpga go golang gpio pmod raspberry-pi raspi verilog webserver xilinx-fpga xilinx-vivado

Last synced: 25 Oct 2024

https://github.com/shyamal-anadkat/wisc-sp13

CS 552 term project : functional design of a microprocessor called the WISC-SP13

cs552 hardware-designs mips-assembly processor processor-architecture verilog verilog-hdl

Last synced: 16 Dec 2024

https://github.com/ekarton/pacman-on-fpga

CSC 258 Final Project: Pacman on an FPGA with Verilog

fpga pacman verilog

Last synced: 24 Nov 2024

https://github.com/rejunity/zero-to-asic-wrapped-parallax

Tiny experimental ASIC design for efabless/OpenLane fab.

asic efabless fpga openlane verilog

Last synced: 24 Nov 2024

https://github.com/carlsagan21/verilog-practice

하시설 이제는 다메요..

verilog

Last synced: 13 Dec 2024

https://github.com/pvgupta24/von-neumann-architecture-cpu

Implementation of 8-Bit CPU based on Von-Neumann Architechture in HDL

cpu cpu-simulator verilog verilog-hdl von-neumann

Last synced: 06 Jan 2025

https://github.com/adamhlt/litex-cva6

LiteX CVA6 - Fixed integration of the CPU into LiteX SoC generator

cva6 fpga litex python verilog

Last synced: 13 Dec 2024

https://github.com/wvangansbeke/smart-card-rsa

RSA alogrithm with hardware/software co-design

rsa-cryptography verilog

Last synced: 27 Dec 2024

https://github.com/ain1084/serial_audio_decoder

Serial audio data (I2S or Left justified) decoder

decoder i2s-audio verilog

Last synced: 20 Dec 2024

https://github.com/rohittp0/chipon

PyTorch to Verilog transpiler

hardware-designs pytorch verilog

Last synced: 31 Oct 2024

https://github.com/sondosaabed/verilog-digital-circuits

Bunch of circuits designed in a Digital Circuits BZU

circuit digital verilog

Last synced: 25 Dec 2024

https://github.com/bartpleiter/fpgc5

A completely self designed (game) computer, implemented in hardware using an FPGA. Basically every component is self designed, from the ISA up to the PCB and software. Project exists to learn more about the fundamentals of computers and to improve my Verilog skills

assembler c compiler computer-architecture cpu fpga gpu hardware software verilog

Last synced: 07 Nov 2024

https://github.com/xtrinch/icestick-fpga-uart

UART + UART packets encoding/decoding + pc reader program for Lattice icestick

fpga icestorm-toolchain verilog

Last synced: 21 Dec 2024

https://github.com/cw1997/verilog-parser

Verilog HDL Parser

parser parsers verilog verilog-hdl verilog-simulator

Last synced: 28 Nov 2024

https://github.com/mattvenn/zero_to_asic_mpw6

MPW6 submission from the Zero to ASIC Course

asic efabless mpw6 sky130 verilog

Last synced: 15 Dec 2024

https://github.com/susiejojo/mips_processor

A simple MIPS processor implemented using Verilog capable of supporting basic I,J and R type instructions. Built using Xilinx Vivado 2019.1

mips mips-architecture processor verilog

Last synced: 17 Dec 2024

https://github.com/dmf444/cscb58-final_project

A (sucessful) attempt at a making guitar hero for a DE2-115 board

altera cscb58 guitar-hero verilog vga

Last synced: 29 Nov 2024

https://github.com/sefakcmn00/fpga-vhdl-samples-

Simple logic gate applications were implemented using FPGA VHDL language. These are; counter counter circuit, float point, multix.

floating-point fpga verilog vhdl

Last synced: 14 Nov 2024

https://github.com/xyene/t258-cpu

A simple RISC CPU implemented in Verilog, as well as compilation toolchain for it.

assembler compiler cpu verilog

Last synced: 18 Nov 2024

https://github.com/UW-PHARM/BitSAD

A domain-specific language for bitstream computing

bitstream code-generation compiler-plugin scala stochastic-computing verilog

Last synced: 15 Oct 2024

https://github.com/kenny2github/v2mc

Synthesize Verilog to Minecraft redstone

hdl minecraft redstone verilog yosys

Last synced: 20 Dec 2024

https://github.com/cheyao/achieve-core

RISC-V SoC + OS

core risc-v soc verilog

Last synced: 04 Jan 2025

https://github.com/kaushalmodi/nim-systemverilog-vpi

Using Nim to interface with Verilog and SystemVerilog test benches via VPI

1364-2005 1800-2017 c cpp nim pli systemverilog verilog vpi

Last synced: 15 Nov 2024

https://github.com/buhe/study_fpga

💾 fpga study with open source tools (on macos)

chisel chisel3 fpga hardware tang-nano verilog

Last synced: 01 Jan 2025

https://github.com/abhishek010397/programming-risc-v

Design of RISC V CPU Core

advanced-computer-architecture microprocessor multithreading python3 risc-v verilog

Last synced: 23 Dec 2024

https://github.com/cepdnaclk/e16-co502-rv32im-pipeline-implementation-group1

The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pipeline CPU supports the entire RV32IM ISA which contains 45 instructions. The designed pipeline CPU was implemented using behavioral modeling in verilogHDL and icarus Verilog was used compile and simulate. gtkWave was used to observe the behavior.

computer-architecture pipeline risc-v rv32im verilog

Last synced: 12 Nov 2024

https://github.com/dvvcz/viva

Experimental cli to create HDL projects using Vivado, outside of their IDE.

cli hardware hdl package-manager rust systemverilog verilog vivado

Last synced: 05 Jan 2025

https://github.com/gogolb/ee175

EE 175 Senior Design. Multibaseline Stereo Camera

computer-vision matlab ov7670 senior-design slam stereo-vision university-course university-project verilog vivado xilinx zynq

Last synced: 01 Dec 2024

https://github.com/jn513/grande-risco-5

Processador RISC-V multi ciclo com implementação RV32I construído em alguns dias de folga.

arquitetura fpga risc-v riscv riscv32 verilog verilog-hdl

Last synced: 15 Dec 2024