https://github.com/daulpavid/verilog_template

Boilerplate project template for verilog that includes directories for simulation, documentation, and formal verification.

cmake verilator verilog verilog-template

Last synced: 15 Jan 2025

https://github.com/algosup/2024-2025-project-1-fpga-team-3

First project of the year 2024-2025

fpga frogger game verilog vga

Last synced: 16 Jan 2025

https://github.com/algosup/2024-2025-project-1-fpga-team-2

fpga verilog

Last synced: 16 Jan 2025

https://github.com/chenqianhe/learnprofessionalbasiccoursesincomputerscience

Learn Professional Basic Courses in Computer Science计算机专业基础课程学习

assembly computer-network computer-science computer-system-structure cpp operating-system principle-of-computer-composition professional-basic-courses verilog

Last synced: 19 Jan 2025

https://github.com/tomarus/midirouter

CMOD-A7 FPGA MIDI Merger/Router/Switch.

fpga midi verilog

Last synced: 08 Feb 2025

https://github.com/samridhisainii/digitaldesign

These are the question of digital design lab from our subject digital design lab which were done in lab

digital-design verilog

Last synced: 28 Jan 2025

https://github.com/akhilrai28/alarm-clock

This project implements a fully functional digital alarm clock using Verilog and Vivado. The design includes features such as setting the time, alarm functionality, and real-time clock display. The project simulates clock timing and alarm triggers, with testbenches for verifying accuracy and reliability on FPGA.

alarm alarm-clock clock fpga hardware real-time simulation testbench verilog vivado

Last synced: 08 Feb 2025

https://github.com/yasnakateb/uartcommunication

☎️ UART Communication Implementation in Verilog HDL

icarus-verilog iverilog serial-communication uart uart-interface uart-protocol uart-verilog verilog

Last synced: 20 Jan 2025

https://github.com/muhammadtalhasami/sv_verilator

System verilog learning journey. Here in this repo you learn about how to write system verilog test bench using verilator tool a c++ test bench. Verilator is basically a 2 state tool .

system-verilog-testbench systemverilog testbench verification verilator- verilator-testbench verilog verilog-hdl

Last synced: 06 Nov 2024

https://github.com/urish/tt05-silife-8x8

Game of Life in Silicon (8x8)

game-of-life tiny-tapeout verilog

Last synced: 11 Jan 2025

https://github.com/risto97/cascade_classifier

Python, C, RTL implementation of Viola Jones cascade classifier, using pretrained model from opencv.

face-detection fpga object-detection pygears python verilog viola-jones

Last synced: 21 Dec 2024

https://github.com/yaxsomo/iris_cubesat

This Repository is dedicated to FPGA development of the IRIS CubeSat

aerospace cubesat fpga free-space-optical-communiucation satellite verilog vhdl vivado xilinx

Last synced: 11 Jan 2025

https://github.com/kyori19/verilog-otp

VerilogHDL implementation of One-Time Password Algorithm (HOTP)

hotp onetimepassword systemverilog verilog verilog-hdl

Last synced: 18 Jan 2025

https://github.com/jgroman/fpga-tangprimer25k-experiments

Learning digital design with Tang Primer 25K

fpga verilog

Last synced: 20 Jan 2025

https://github.com/lebrancconvas/verilog-playground

Verilog Playground.

digital-electronics logic-gates verilog

Last synced: 08 Jan 2025

https://github.com/viktor-prutyanov/fpga-ir

IR receiver with UART interface

fpga ir-receiver remote-control verilog

Last synced: 05 Feb 2025

https://github.com/yugr/gatecheck

Yet another Verilog static analyzer

clock-g gating static-analysis static-analyzer verilog

Last synced: 27 Dec 2024

https://github.com/niedzielski/swankmania

Graphics processor and ACX705AKM LCD driver hardware implementation and misc.

fpga game gpu hdl verilog

Last synced: 02 Feb 2025

https://github.com/aben20807/computer_organization

1052_計算機組織 COMPUTER ORGANIZATION

cache cpu datapath pipeline single-cycle verilog

Last synced: 16 Jan 2025

https://github.com/sahilmgandhi/m152b-fall2018

CS M152B Codebase Fall 2018

c color-recognition gyroscope hdmi microblaze verilog xilinx-fpga

Last synced: 10 Jan 2025

https://github.com/suda-morris/suda_riscv

Playing with FPGA and RISC-V

chisel3 fpga risc-v verilog

Last synced: 30 Dec 2024

https://github.com/kkkaan/metu-ceng-thes

Some of the homeworks I have done at metu ceng.

bash c clingo cpp haskell java prolog python quantum-computing verilog

Last synced: 04 Jan 2025

https://github.com/standardsemiconductor/veldt-blinker-verilog

VELDT blinker example with verilog

veldt verilog

Last synced: 11 Jan 2025

https://github.com/engineersbox/cbox16-processor

Implementation of QuAC v1.0 ISA microarchitecture called CBox16

arm armv7 cbox16 cpu isa microarchitecture mips mipsiv quac verilog vhdl

Last synced: 27 Jan 2025

https://github.com/bucknalla/warc_fusesoc

WARC Open Fusesoc Cores Repository

hls ip migen open-cores verilog

Last synced: 09 Jan 2025

https://github.com/bucknalla/axis-interfacer

Extract AXI (Full, Lite and Stream) interfaces from Verilog source files

axi axi-lite axis verilog xilinx

Last synced: 09 Jan 2025

https://github.com/mgriebling/lola

A digital design language by Nicklaus Wirth, similar to VHDL and Verilog, but much simpler and easier to master.

circuit-compiler digital-circuit-design lola simulator swift verilog vhdl wirth

Last synced: 29 Dec 2024

https://github.com/vivekadi/fpga_verilog_interfacing

Interfacing peripherals to FPGA

fpga interfacing keypad4x4 labs motor-controller singal-generator spartan6 verilog xilinx

Last synced: 14 Jan 2025

https://github.com/acmachado14/circuitoscombinacionais

Circuitos Combinacionais em Verilog | Trabalho pratico pra disciplina de Introdução aos Sistemas Lógicos - UFV

verilog

Last synced: 21 Jan 2025

https://github.com/brlin-tw/clean-filter-for-verilog

Clean your Verilog design code!

bash clean-filter filter git git-attributes istyle vdent verilog

Last synced: 22 Jan 2025

https://github.com/chrnthnkmutt/carpark_verilog

This project is using for illustrating on making the circuit on Xillin's BASYS3 from AMD and Verilog Language on Vivado, on the scope of car parking system

basys3 basys3-fpga fpga verilog verilog-code verilog-project

Last synced: 14 Jan 2025

https://github.com/zazi2002/computer-architectur-lab

Computer Architecture Lab projects with various fundamental concepts, including multi-cycle MIPS processors and PIC32 microcontroller programming.

counter mips multicycle-processor pic32 verilog

Last synced: 28 Dec 2024

https://github.com/harshalmittal4/24-bit-risc-processor

Computer Architecture-MIPS Processor simulation in verilog with self developed ISA

isa risc-processor verilog

Last synced: 20 Jan 2025

https://github.com/valaphee/redsynth

Generate redstone circuits out of Verilog.

bukkit-plugin fpga minecraft redstone synthesis verilog

Last synced: 07 Jan 2025

https://github.com/blagojeblagojevic/vga_verilog

Implementation of a vga interface on a Basys 3 FPGA

fpga verilog

Last synced: 21 Dec 2024

https://github.com/xtrinch/icestick-fpga-example

Example project for Lattice icestick fpga

fpga icestorm-toolchain verilog

Last synced: 21 Dec 2024

https://github.com/euripedesrocha/tbpp

A simple test library for verilator

cpp fusesoc verilator verilog

Last synced: 28 Jan 2025

https://github.com/zhb2000/computerorganizationexperiment

计算机组成与设计课程实验

computer-organization verilog

Last synced: 25 Dec 2024

https://github.com/hugech38/mips

🐢 用 Verilog 实现的单周期 MIPS 指令集的 CPU，并用它来计算斐波那契数。

cpu mips mips-architecture mips-instructions mips-processor verilog vhdl

Last synced: 21 Jan 2025

https://github.com/mat1g3r/csc258_final_project

CSC258 final project

verilog

Last synced: 23 Jan 2025

https://github.com/rosscomputerguy/slimproc

SlimProc is a 32-bit RISC instruction set

cpu-emulator fpga processor verilog

Last synced: 19 Jan 2025

https://github.com/ethanuppal/hardfloat-spade

Spade wrappers for the Berkley Hardfloat floating-point library

berkeley floating-point hardware verilog

Last synced: 07 Feb 2025

https://github.com/vitalyankh/open-fpga-tutorial

Open FPGA Tutorial

chisel fpga verilog

Last synced: 11 Jan 2025

https://github.com/ellisgl/addressable-debouncer-verilog

Addressable 8 SPDT debouncer in Verilog

cpld debounce debounce-button debouncing fpga verilog

Last synced: 19 Jan 2025

https://github.com/jn513/estudos_verilog

Exemplos feito em verilog para estudos

fpga fpga-programming hardware verilog verilog-code verilog-hdl

Last synced: 08 Feb 2025

https://github.com/a-bdellatif/frequencydivider

verilog code for frequency divider circuit implemented with verilog hdl

digital-design fpga frequency-divider hardware-description-language hdl verilog

Last synced: 03 Feb 2025

https://github.com/jn513/baby-risco-5

Multi-cycle RISC-V processor with RV32E implementation

riscv riscv32 riscv32e verilog verilog-hdl

Last synced: 08 Feb 2025

https://github.com/a-bdellatif/sequencedetector

11001 sequence detector

asic digital-design fpga hardware hardware-description-language hdl sequence-detection sequence-detector verilog

Last synced: 03 Feb 2025

https://github.com/dyna-bytes/fisr

Specialized FPU for Fast Inverse Square Root Algorithm

floating-point fpu hardware-acceleration verilog

Last synced: 30 Jan 2025

https://github.com/rambodrahmani/dalle_porte_and_or_not_al_sistema_calcolatore

Dalle Porte AND OR NOT Al Sistema Calcolatore. Un viaggio nel mondo delle reti logiche in campagnia del linguaggio Verilog.

altera boolean-algebra boolean-logic logic-gates modelsim verilog

Last synced: 29 Dec 2024

https://github.com/rauhul/ece385

Digital Systems Laboratory UIUC FA 2016

altera fpga quartus-prime systemverilog verilog

Last synced: 29 Jan 2025

https://github.com/abdallahabusedo/cmp305-introduction-verilog

introduction to Verilog in Integrated Circuit Design And VLSI technology

verilog verilog-code verilog-hdl verilog-project

Last synced: 13 Dec 2024

https://github.com/melchisedech333/verilog-experiments

:space_invader: My studies with Verilog and notions of digital systems.

digital-system-design digital-systems digital-systems-design digital-systems-fundamentals hdl icarus-verilog verilog verilog-code verilog-examples verilog-hdl verilog-project

Last synced: 03 Feb 2025

https://github.com/mummanajagadeesh/improve

Image processing using Verilog

digital digital-image-processing edge-detection edge-detection-algorithms filtering-algorithm filters geometric-transformations hdl image-filters image-processing masks morphological-operators noise-reduction verilog verilog-hdl

Last synced: 06 Feb 2025

https://github.com/ain1084/dual_clock_buffer

Dual clock buffer for modules connected by valid-ready protocol

protocol-buffers verilog

Last synced: 20 Dec 2024

https://github.com/dyna-bytes/fpga_winter_internship_2020

[Korea University Elementary Particle Physics Lab] Hardware control research using FPGA

fpga rtl verilog vhdl

Last synced: 30 Jan 2025

https://github.com/ain1084/serial_audio_encoder

Serial audio encoder

encoder i2s-audio verilog

Last synced: 20 Dec 2024

https://github.com/abdallahabusidu/cmp305-introduction-verilog

introduction to Verilog in Integrated Circuit Design And VLSI technology

verilog verilog-code verilog-hdl verilog-project

Last synced: 06 Feb 2025

https://github.com/cmpark0126/mips_32bits

Implements 32bits MIPS with verilog. (18.11.25 ~ 18.12.)

fpga mips32cpu verilog

Last synced: 23 Dec 2024

https://github.com/shuregg/riscv-simple-cpu

Creating a risc-v processor

cpu risc-v riscv riscv32 rtl systemverilog verification verilog verilog-hdl

Last synced: 06 Feb 2025

https://github.com/junzhengca/space-enemies

Rip off of space invaders coded in Verilog with VGA output support, intended for DE2-115 FPGA board. Final project for CSCB58.

assignment de2-115 hardware project verilog

Last synced: 06 Feb 2025

https://github.com/wpmed92/takerisc

A RISC-V RV32I Core written in TL-Verilog

hardware riscv riscv32 tl-verilog verilog

Last synced: 03 Feb 2025

https://github.com/jasonbrave/microsoc

RISC-V SoC

microcontroller risc-v riscv soc system-on-chip systemverilog uart verilog

Last synced: 20 Dec 2024

https://github.com/soham9284/100_days_of_verilog

verilog verilog-hdl vlsi-design xilinx-vivado

Last synced: 02 Feb 2025

https://github.com/sergz72/fpga

FPGA related stuff

assembler assembly-language bytecode-compiler cpu cyclone forth forth-cpu forth-language fpga fpga-programming gowin java java-cpu risc-v verilog

Last synced: 26 Jan 2025

https://github.com/bilalm04/combination-lock-fsm

Moore FSM combination lock in Verilog for DE1-SOC Board.

de1-soc hardware verilog

Last synced: 31 Dec 2024

https://github.com/pseudoincorrect/fpga_mcu_wifi

Link between a PC and a FPGA through wifi

c fpga socket verilog wifi

Last synced: 16 Dec 2024

https://github.com/rishabh-agarwal/cisc530-computersystemarchitecture

This repository contain HW and assignment for ComputerSystemArchitecture class at Harrisburg University

assignment cisc530 harrisburg homework kapila university verilog

Last synced: 28 Dec 2024

https://github.com/weisrc/fpgaudio

MIDI file to Verilog Code Generation - FPGAudio!

midi verilog

Last synced: 23 Dec 2024

https://github.com/weisrc/nesv

NESystem Verilog

basys3 emscripten emulator fpga nes systemverilog verilator verilog vivado webassembly

Last synced: 23 Dec 2024

https://github.com/pavlostzitzos/hdls-intro

SystemVerilog , Verilog , Verilog-A , Verilog-AMS tutorial

verilog verilog-hdl verilog-testbenches vhdl

Last synced: 24 Dec 2024

https://github.com/xilover/iot-and-edge-computing

Hands-on learning experience in IoT, edge computing, and embedded systems using a variety of platforms such as microcontrollers (nRF, STM32, ESP32), FPGAs (Xilinx), and SoCs (Raspberry Pi, Zynq).

aws-iot azure-iot ble circuit-design edge-computing esp32 fpga iot mqtt nrf pynq-z2 raspberry-pi rtos stm32 system-on-chip verilog vhdl vivado xilinx xilinx-zynq

Last synced: 18 Dec 2024

https://github.com/alyssonmach/sistema-seguranca-residencial

Projeto final da disciplina Laboratório de Circuitos Lógicos - Sistema de Segurança Residencial.

logic-circuit logic-gates logisim project ufcg verilog

Last synced: 24 Dec 2024

https://github.com/drom/vpreproc

Verilog preprocessor bindings for Node.js

napi nodejs preprocessor verilog

Last synced: 18 Dec 2024

https://github.com/calint/zen-x

experimental retro 16 bit cpu written in verilog xilinx vivado intended for fpga Cmod S7 from Digilent

16-bit cmod-s7 cpu fpga verilog vintage vivado xilinx

Last synced: 10 Jan 2025

https://github.com/sameer/de2-115-template

HDLMake template for terasIC DE2-115

de2-115 hdlmake template verilog vhdl

Last synced: 18 Dec 2024

https://github.com/tmahlburg/mriscv

simple, modular rv32i implementation (WIP)

risc-v riscv riscv32 rv32i verilog verilog-hdl

Last synced: 17 Jan 2025

https://github.com/tmahlburg/picosoc-basys3

Wrapper module for the PicoSoC to support the Digilent Basys 3

artix artix-7 basys3 digilent picorv32 picosoc risc-v verilog vivado xilinx

Last synced: 17 Jan 2025

https://github.com/adolbyb/vhdl-fpga-nexys-a7

A collection of code from CDA 4240C: Design of Digital System and Lab

artix-7 fpga hardware-description-language hdl nexys-a7 verilog vhdl xilinx-vivado

Last synced: 20 Jan 2025

https://github.com/muhammadtalhasami/rtl_practice

This repository contain basic verilog codes which include the implementation of DLD (digital logic desgin ) circuits.

100daysofrtl hardware-coding muhammadtalhasami-github- rtl testbench verilog verilog-practice vhdl

Last synced: 25 Dec 2024

https://github.com/the-pinbo/risc-spm

This project involves the development and enhancement of a RISC Stored-Program Machine (RISC SPM), based on the architecture detailed in "Advanced Digital Design with the Verilog HDL" by Michael D. Ciletti.

computer-architecture riscv verilog

Last synced: 25 Dec 2024

https://github.com/tdjsnelling/garbled-circuits

Yao’s Garbled Circuits in TypeScript

cryptography garbled-circuits javascript mpc multiparty-computation nodejs oblivious-transfer typescript verilog

Last synced: 08 Feb 2025

https://github.com/marialmeida1/study-ac

Atividades de Arquitetura de Computadores 1

arquitetura-de-computadores java python verilog

Last synced: 05 Jan 2025

https://github.com/skpro-glitch/riscv-processor-asic

This is a basic RISC-V based processor under development. It follows the 32-bit Integer ISA.

asic asic-design asic-verification fpga hardware-designs open-source openlane openlane-flow processor-architecture processor-design risc-v riscv32 verilog verilog-hdl vlsi vlsi-design

Last synced: 20 Dec 2024

https://github.com/tm90/verilogmodules

generic Verilog modules for reuse...

generic-verilog-modules systemverilog verilog

Last synced: 13 Jan 2025

https://github.com/dvvcz/cpe-133

icarus-verilog iverilog systemverilog verilog vivado

Last synced: 05 Jan 2025

https://github.com/byte-me404/tt-ps2-morse-encoder

Custom ASIC design which decodes a PS/2 keyboard, furthermore it encodes and outputs the data as morse code

asic morse-code ps2-keyboard tinytapeout verilog

Last synced: 05 Jan 2025

https://github.com/lemongrb/sequencedetector

11001 sequence detector

asic digital-design fpga hardware hardware-description-language hdl sequence-detection sequence-detector verilog

Last synced: 10 Jan 2025

https://github.com/lemongrb/frequencydivider

verilog code for frequency divider circuit implemented with verilog hdl

digital-design fpga frequency-divider hardware-description-language hdl verilog

Last synced: 10 Jan 2025

https://github.com/marceldobehere/goofy-cpu-verilog

cpu cpu-simulator goofy goofy-cpu sim verilog

Last synced: 04 Jan 2025

https://github.com/kar-dim/icsd-digitalsystems

Some Verilog projects, implemented as part of my university coursework (2013-2019, Information and Communications Systems Engineering, University of the Aegean).

verilog

Last synced: 04 Jan 2025

https://github.com/francoriba/alu-uart-basys3

UART modules interface using Verilog for the Basys3 board (Digilent). Computer Architecture 2023. FCEFyN, UNC, Argentina

arquitectura-de-computadores basys3-fpga computerarchitecture fcefyn hardwaredescription uart unc verilog

Last synced: 11 Jan 2025

https://github.com/anuragnatoo/ele301p

VLSI System Design Practice Lab

activity-factors practice-lab python python-application test-bench verilog vlsi

Last synced: 11 Jan 2025

https://github.com/vincent-g-van/one-time-pad-fpga

64-Bits One-Time Pad on FPGA Board (Nexys 4 DDR Artix-7).

diligent nexys4 one-time-pad otp seven-segment verilog vivado

Last synced: 30 Jan 2025

https://github.com/sofiavalos/verilog_ethernet_10g_pcs

Bloques y bancos de pruebas PCS para Ethernet 10G.

ethernet pcs verilog

Last synced: 05 Jan 2025

https://github.com/hiyouga/digic-experiment

BUAA CST Autumn 2018 Digital Circuit Experiment

digital-circuit verilog

Last synced: 05 Jan 2025

https://github.com/awrsha/digital-systems

Digital systems lesson with Dr. Vahid Rostami Provided by Qazvin Islamic Azad University

digital-systems-design verilog vhdl-examples

Last synced: 12 Jan 2025

https://github.com/mattjesc/uart-cdc-design

UART Design with CDC, FIFO Buffers, and Dynamic Baud Rate Configuration

cdc fifo fpga uart verilog vivado

Last synced: 18 Jan 2025

https://github.com/rithwikksvr/verilog-snake-game

Last semester we made a Snake Game implemented on Hardware. For this Purpose we used Basys 2 Spartan-3E FPGA, 7x5 LED Matrix and Verilog Programming.

fpga verilog

Last synced: 12 Jan 2025

https://github.com/amir78729/logical-circuits-course-final-project

My Logical Circuits course Final Project - Fall98(2019) - VERILOG

logical-circuits verilog

Last synced: 18 Jan 2025