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Verilog
Verilog is a widely-used hardware description language (HDL) that enables designers to model, simulate, and synthesize digital circuits. It provides a text-based format for specifying the structure and behavior of electronic systems, making it easier to design complex hardware components such as microprocessors, memory, and communication devices.
- GitHub: https://github.com/topics/verilog
- Wikipedia: https://en.wikipedia.org/wiki/Verilog
- Aliases: hdl, hardware-description-language,
- Last updated: 2025-02-08 00:27:45 UTC
- JSON Representation
https://github.com/kareimgazer/pci_target_device
Verilog simulation for a Target Device on a PCI bus with read and write transactions.
pci pci-devices verilog xilin xilinx-vivado
Last synced: 03 Feb 2025
https://github.com/samridhisainii/digitaldesign
These are the question of digital design lab from our subject digital design lab which were done in lab
Last synced: 28 Jan 2025
https://github.com/namberino/nam85
An 8085-based Computer
8085 computer-architecture digital-logic fpga verilog
Last synced: 20 Jan 2025
https://github.com/viktor-prutyanov/fpga-ir
IR receiver with UART interface
fpga ir-receiver remote-control verilog
Last synced: 05 Feb 2025
https://github.com/ashkan-khd/conways-game-of-life-verilog
An easy approach for Conway's Game Of Life with Verilog HDL
conways-game-of-life conways-game-of-life-verilog game-of-life game-of-life-verilog testbench verilog verilog-game-of-life verilog-hdl
Last synced: 20 Dec 2024
https://github.com/bryanlimy/flappybird-verilog
Flappy-Bird-liked game in Verilog
flappy-bird flappy-bird-game verilog
Last synced: 09 Feb 2025
https://github.com/meetps/ee-214
VHDL and Verilog Codes for Digital Lab.
digital-logic fpga verilog vhdl
Last synced: 04 Jan 2025
https://github.com/tomarus/midirouter
CMOD-A7 FPGA MIDI Merger/Router/Switch.
Last synced: 08 Feb 2025
https://github.com/cpehle/cascade
Cycle based C++ hardware simulation infrastructure
Last synced: 08 Feb 2025
https://github.com/akhilrai28/alarm-clock
This project implements a fully functional digital alarm clock using Verilog and Vivado. The design includes features such as setting the time, alarm functionality, and real-time clock display. The project simulates clock timing and alarm triggers, with testbenches for verifying accuracy and reliability on FPGA.
alarm alarm-clock clock fpga hardware real-time simulation testbench verilog vivado
Last synced: 08 Feb 2025
https://github.com/muhammadtalhasami/sv_verilator
System verilog learning journey. Here in this repo you learn about how to write system verilog test bench using verilator tool a c++ test bench. Verilator is basically a 2 state tool .
system-verilog-testbench systemverilog testbench verification verilator- verilator-testbench verilog verilog-hdl
Last synced: 06 Nov 2024
https://github.com/daulpavid/verilog_template
Boilerplate project template for verilog that includes directories for simulation, documentation, and formal verification.
cmake verilator verilog verilog-template
Last synced: 15 Jan 2025
https://github.com/shyamal-anadkat/the-11-of-us
adc ece551 flight-controller hdl integrator quadcopter synthesis system-verilog uart verilog vhdl
Last synced: 08 Feb 2025
https://github.com/alyssonmach/logic-circuits
Simulations made in the UFCG logic circuit laboratory.
laboratory logic-circuit logisim quartus ufcg verilog
Last synced: 24 Dec 2024
https://github.com/byte-me404/jku-tt06-ps2-morse-encoder
Custom ASIC design which decodes a PS/2 keyboard, furthermore it encodes and outputs the data as morse code
asic ps2-keyboard tinytapeout verilog
Last synced: 05 Jan 2025
https://github.com/eomielan/16-bit-risc-machine
16-bit CPU architecture implementation and verification using SystemVerilog
cpu-architecture systemverilog verilog
Last synced: 30 Dec 2024
https://github.com/hywooo/docker-bsv-wsl2
🐋Docker for Bluespec SystemVerilog (BSV) on WSL2, compatible with WangXuan95/BSV_Tutorial_cn. 适用于BSV中文教程的Docker BSV （WSL2）环境。
bluespec-systemverilog bsv docker dockerfile packages systemverilog verilog vivado
Last synced: 29 Oct 2024
https://github.com/gyeonghokim/riscv_core
building 32bit risc-v core and Machine Learning for Branch Prediction
Last synced: 29 Dec 2024
https://github.com/pirate-emperor/cipherx
CipherX is a verification project for Advanced Encryption Standard (AES-128) using Universal Verification Methodology (UVM). It leverages Verilog, SystemVerilog, and Python to ensure robust encryption algorithm validation, integrating comprehensive UVM components and tests.
aes-128 cryptography cryptography-algorithms dataencryption dataencryptionstandards digitaldesign encrytption hardwareverification python security testing-framework uvm verification verilog
Last synced: 04 Dec 2024
https://github.com/yugr/gatecheck
Yet another Verilog static analyzer
clock-g gating static-analysis static-analyzer verilog
Last synced: 27 Dec 2024
https://github.com/francoriba/alu-uart-basys3
UART modules interface using Verilog for the Basys3 board (Digilent). Computer Architecture 2023. FCEFyN, UNC, Argentina
arquitectura-de-computadores basys3-fpga computerarchitecture fcefyn hardwaredescription uart unc verilog
Last synced: 11 Jan 2025
https://github.com/kar-dim/icsd-digitalsystems
Some Verilog projects, implemented as part of my university coursework (2013-2019, Information and Communications Systems Engineering, University of the Aegean).
Last synced: 04 Jan 2025
https://github.com/shuregg/riscv-simple-cpu
Creating a risc-v processor
cpu risc-v riscv riscv32 rtl systemverilog verification verilog verilog-hdl
Last synced: 06 Feb 2025
https://github.com/rosscomputerguy/slimproc
SlimProc is a 32-bit RISC instruction set
cpu-emulator fpga processor verilog
Last synced: 19 Jan 2025
https://github.com/weisrc/fpgaudio
MIDI file to Verilog Code Generation - FPGAudio!
Last synced: 23 Dec 2024
https://github.com/marceldobehere/goofy-cpu-verilog
cpu cpu-simulator goofy goofy-cpu sim verilog
Last synced: 04 Jan 2025
https://github.com/vivekadi/fpga_verilog_interfacing
Interfacing peripherals to FPGA
fpga interfacing keypad4x4 labs motor-controller singal-generator spartan6 verilog xilinx
Last synced: 14 Jan 2025
https://github.com/blagojeblagojevic/vga_verilog
Implementation of a vga interface on a Basys 3 FPGA
Last synced: 21 Dec 2024
https://github.com/ellisgl/addressable-debouncer-verilog
Addressable 8 SPDT debouncer in Verilog
cpld debounce debounce-button debouncing fpga verilog
Last synced: 19 Jan 2025
https://github.com/sauravmaheshkar/verilog-template
❄️ Template for Verilog Projects using iverilog and gtkwave (nix devShell supported)
hardware-description-language template-project verilog verilog-template vhdl
Last synced: 01 Feb 2025
https://github.com/drom/vpreproc
Verilog preprocessor bindings for Node.js
napi nodejs preprocessor verilog
Last synced: 10 Feb 2025
https://github.com/junzhengca/space-enemies
Rip off of space invaders coded in Verilog with VGA output support, intended for DE2-115 FPGA board. Final project for CSCB58.
assignment de2-115 hardware project verilog
Last synced: 06 Feb 2025
https://github.com/lemongrb/frequencydivider
verilog code for frequency divider circuit implemented with verilog hdl
digital-design fpga frequency-divider hardware-description-language hdl verilog
Last synced: 10 Jan 2025
https://github.com/lemongrb/sequencedetector
11001 sequence detector
asic digital-design fpga hardware hardware-description-language hdl sequence-detection sequence-detector verilog
Last synced: 10 Jan 2025
https://github.com/jn513/estudos_verilog
Exemplos feito em verilog para estudos
fpga fpga-programming hardware verilog verilog-code verilog-hdl
Last synced: 08 Feb 2025
https://github.com/zazi2002/computer-architectur-lab
Computer Architecture Lab projects with various fundamental concepts, including multi-cycle MIPS processors and PIC32 microcontroller programming.
counter mips multicycle-processor pic32 verilog
Last synced: 28 Dec 2024
https://github.com/bucknalla/warc_fusesoc
WARC Open Fusesoc Cores Repository
hls ip migen open-cores verilog
Last synced: 09 Jan 2025
https://github.com/vgalovic/hdl_examples
A collection of VHDL and Verilog examples organized by language and practice section, with setup.tcl files for easy Vivado setup. These examples reflect my FPGA development practice and learning.
Last synced: 03 Jan 2025
https://github.com/rehankarthikchandralal/implementation-of-a-configurable-neural-processing-unit-with-input-and-weight-stationary-dataflows
Used Verilog to design an entire NPU that supports two different kinds of dataflows to enable data reuse in order to reduce power consumption and resource utilization
neural-network-hardware verilog
Last synced: 09 Feb 2025
https://github.com/wpmed92/takerisc
A RISC-V RV32I Core written in TL-Verilog
hardware riscv riscv32 tl-verilog verilog
Last synced: 03 Feb 2025
https://github.com/jn513/baby-risco-5
Multi-cycle RISC-V processor with RV32E implementation
riscv riscv32 riscv32e verilog verilog-hdl
Last synced: 08 Feb 2025
https://github.com/acmachado14/circuitoscombinacionais
Circuitos Combinacionais em Verilog | Trabalho pratico pra disciplina de Introdução aos Sistemas Lógicos - UFV
Last synced: 21 Jan 2025
https://github.com/mgriebling/lola
A digital design language by Nicklaus Wirth, similar to VHDL and Verilog, but much simpler and easier to master.
circuit-compiler digital-circuit-design lola simulator swift verilog vhdl wirth
Last synced: 29 Dec 2024
https://github.com/adolbyb/vhdl-fpga-nexys-a7
A collection of code from CDA 4240C: Design of Digital System and Lab
artix-7 fpga hardware-description-language hdl nexys-a7 verilog vhdl xilinx-vivado
Last synced: 20 Jan 2025
https://github.com/hiyouga/digic-experiment
BUAA CST Autumn 2018 Digital Circuit Experiment
Last synced: 05 Jan 2025
https://github.com/melchisedech333/verilog-experiments
:space_invader: My studies with Verilog and notions of digital systems.
digital-system-design digital-systems digital-systems-design digital-systems-fundamentals hdl icarus-verilog verilog verilog-code verilog-examples verilog-hdl verilog-project
Last synced: 03 Feb 2025
https://github.com/dyna-bytes/fisr
Specialized FPU for Fast Inverse Square Root Algorithm
floating-point fpu hardware-acceleration verilog
Last synced: 30 Jan 2025
https://github.com/quentinwach/computer-engineering
📝 Notes on computer engineering. From application to custom computer design.
book computer-architecture course cpu cpu-architecture documentation gtkwave hack hack-computer icarus icarus-verilog iverilog logisim nand2tetris nand2tetris-assignments nand2tetris-projects nand2tetris-solutions recources verilog
Last synced: 12 Jan 2025
https://github.com/brlin-tw/clean-filter-for-verilog
Clean your Verilog design code!
bash clean-filter filter git git-attributes istyle vdent verilog
Last synced: 22 Jan 2025
https://github.com/bilalm04/combination-lock-fsm
Moore FSM combination lock in Verilog for DE1-SOC Board.
Last synced: 31 Dec 2024
https://github.com/alyssonmach/sistema-seguranca-residencial
Projeto final da disciplina Laboratório de Circuitos Lógicos - Sistema de Segurança Residencial.
logic-circuit logic-gates logisim project ufcg verilog
Last synced: 24 Dec 2024
https://github.com/chrnthnkmutt/carpark_verilog
This project is using for illustrating on making the circuit on Xillin's BASYS3 from AMD and Verilog Language on Vivado, on the scope of car parking system
basys3 basys3-fpga fpga verilog verilog-code verilog-project
Last synced: 14 Jan 2025
https://github.com/rauhul/ece385
Digital Systems Laboratory UIUC FA 2016
altera fpga quartus-prime systemverilog verilog
Last synced: 29 Jan 2025
https://github.com/xilover/iot-and-edge-computing
Hands-on learning experience in IoT, edge computing, and embedded systems using a variety of platforms such as microcontrollers (nRF, STM32, ESP32), FPGAs (Xilinx), and SoCs (Raspberry Pi, Zynq).
aws-iot azure-iot ble circuit-design edge-computing esp32 fpga iot mqtt nrf pynq-z2 raspberry-pi rtos stm32 system-on-chip verilog vhdl vivado xilinx xilinx-zynq
Last synced: 18 Dec 2024
https://github.com/mummanajagadeesh/i2c-protocol-verilog
Verilog Implementation of I2C Protocol using Finite State Machine (FSM) design
finite-state-machine fpga fsm i2c i2cprotocol verilog verilog-hdl verilog-project xilinx xilinx-vivado
Last synced: 25 Jan 2025
https://github.com/tdjsnelling/garbled-circuits
Yao’s Garbled Circuits in TypeScript
cryptography garbled-circuits javascript mpc multiparty-computation nodejs oblivious-transfer typescript verilog
Last synced: 08 Feb 2025
https://github.com/a-bdellatif/frequencydivider
verilog code for frequency divider circuit implemented with verilog hdl
digital-design fpga frequency-divider hardware-description-language hdl verilog
Last synced: 03 Feb 2025
https://github.com/chayashri2308/vending_machine
A simple Vending Machine design for only one product using Verilog. The user can enter three different currency notes and based on the price of the product, the machine dispenses the product and gives the change.
Last synced: 31 Jan 2025
https://github.com/hugech38/mips
🐢 用 Verilog 实现的单周期 MIPS 指令集的 CPU，并用它来计算斐波那契数。
cpu mips mips-architecture mips-instructions mips-processor verilog vhdl
Last synced: 21 Jan 2025
https://github.com/yasnakateb/sdramcontroller
🛠 A SDRAM controller in Verilog HDL
icarus-verilog iverilog memory-controller sdram sdram-controller verilog verilog-hdl
Last synced: 20 Jan 2025
https://github.com/pavlostzitzos/hdls-intro
SystemVerilog , Verilog , Verilog-A , Verilog-AMS tutorial
verilog verilog-hdl verilog-testbenches vhdl
Last synced: 24 Dec 2024
https://github.com/standardsemiconductor/veldt-blinker-verilog
VELDT blinker example with verilog
Last synced: 11 Jan 2025
https://github.com/liu42/pipeline
《计算机组成原理》课程设计，基于 MIPS 系统的流水线 CPU 设计
architecture computer-architecture course-project cpu fpga homework-project mips mips-architecture mips-processor pipeline verilog
Last synced: 23 Nov 2024
https://github.com/marialmeida1/study-ac
Atividades de Arquitetura de Computadores 1
arquitetura-de-computadores java python verilog
Last synced: 05 Jan 2025
https://github.com/jasonbrave/microsoc
RISC-V SoC
microcontroller risc-v riscv soc system-on-chip systemverilog uart verilog
Last synced: 20 Dec 2024
https://github.com/ellisgl/driver-yl-3
Verilog code to run the YL-3 8 digit 7 segment display.
Last synced: 19 Jan 2025
https://github.com/skpro-glitch/riscv-processor-asic
This is a basic RISC-V based processor under development. It follows the 32-bit Integer ISA.
asic asic-design asic-verification fpga hardware-designs open-source openlane openlane-flow processor-architecture processor-design risc-v riscv32 verilog verilog-hdl vlsi vlsi-design
Last synced: 20 Dec 2024
https://github.com/mummanajagadeesh/improve
Image processing using Verilog
digital digital-image-processing edge-detection edge-detection-algorithms filtering-algorithm filters geometric-transformations hdl image-filters image-processing masks morphological-operators noise-reduction verilog verilog-hdl
Last synced: 06 Feb 2025
https://github.com/the-pinbo/risc-spm
This project involves the development and enhancement of a RISC Stored-Program Machine (RISC SPM), based on the architecture detailed in "Advanced Digital Design with the Verilog HDL" by Michael D. Ciletti.
computer-architecture riscv verilog
Last synced: 25 Dec 2024
https://github.com/muhammadtalhasami/rtl_practice
This repository contain basic verilog codes which include the implementation of DLD (digital logic desgin ) circuits.
100daysofrtl hardware-coding muhammadtalhasami-github- rtl testbench verilog verilog-practice vhdl
Last synced: 25 Dec 2024
https://github.com/ethanuppal/hardfloat-spade
Spade wrappers for the Berkley Hardfloat floating-point library
berkeley floating-point hardware verilog
Last synced: 07 Feb 2025
https://github.com/byte-me404/tt-ps2-morse-encoder
Custom ASIC design which decodes a PS/2 keyboard, furthermore it encodes and outputs the data as morse code
asic morse-code ps2-keyboard tinytapeout verilog
Last synced: 05 Jan 2025
https://github.com/ain1084/dual_clock_buffer
Dual clock buffer for modules connected by valid-ready protocol
Last synced: 20 Dec 2024
https://github.com/sofiavalos/verilog_ethernet_10g_pcs
Bloques y bancos de pruebas PCS para Ethernet 10G.
Last synced: 05 Jan 2025
https://github.com/eshansurendra/uart-fpga
This repository documents a project undertaken as part of the EN2111 Electronic Circuit Design module at the University of Moratuwa, focusing on the implementation of a UART communication link between two FPGA boards.
digital-design embedded-systems fpga quartus-prime systemverilog-hdl testbench uart verilog
Last synced: 18 Jan 2025
https://github.com/abtinz/logic-circuits-final-project
Aut Logic Circuits Finall Project Fall 1400
Last synced: 12 Jan 2025
https://github.com/soham9284/100_days_of_verilog
verilog verilog-hdl vlsi-design xilinx-vivado
Last synced: 02 Feb 2025
https://github.com/sergz72/fpga
FPGA related stuff
assembler assembly-language bytecode-compiler cpu cyclone forth forth-cpu forth-language fpga fpga-programming gowin java java-cpu risc-v verilog
Last synced: 26 Jan 2025
https://github.com/valaphee/redsynth
Generate redstone circuits out of Verilog.
bukkit-plugin fpga minecraft redstone synthesis verilog
Last synced: 07 Jan 2025
https://github.com/abdallahabusedo/cmp305-introduction-verilog
introduction to Verilog in Integrated Circuit Design And VLSI technology
verilog verilog-code verilog-hdl verilog-project
Last synced: 13 Dec 2024
https://github.com/amir78729/logical-circuits-course-final-project
My Logical Circuits course Final Project - Fall98(2019) - VERILOG
Last synced: 18 Jan 2025
https://github.com/rithwikksvr/verilog-snake-game
Last semester we made a Snake Game implemented on Hardware. For this Purpose we used Basys 2 Spartan-3E FPGA, 7x5 LED Matrix and Verilog Programming.
Last synced: 12 Jan 2025
https://github.com/chayashri2308/parking_management
Parking Management System using Verilog, to identify the occupied and vacant space in a parking lot.
Last synced: 31 Jan 2025
https://github.com/awrsha/digital-systems
Digital systems lesson with Dr. Vahid Rostami Provided by Qazvin Islamic Azad University
digital-systems-design verilog vhdl-examples
Last synced: 12 Jan 2025
