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Verilog

Verilog is a widely-used hardware description language (HDL) that enables designers to model, simulate, and synthesize digital circuits. It provides a text-based format for specifying the structure and behavior of electronic systems, making it easier to design complex hardware components such as microprocessors, memory, and communication devices.

https://github.com/urish/tt05-silife-8x8

Game of Life in Silicon (8x8)

game-of-life tiny-tapeout verilog

Last synced: 11 Jan 2025

https://github.com/kitune-san/kfpcjr

[WIP] PoC

fpga pcjr verilog

Last synced: 21 Jan 2025

https://github.com/kareimgazer/pci_target_device

Verilog simulation for a Target Device on a PCI bus with read and write transactions.

pci pci-devices verilog xilin xilinx-vivado

Last synced: 03 Feb 2025

https://github.com/djg/cpu

CPU - Verilog + Rust

cmake fpga rtl rust verilator verilog

Last synced: 19 Dec 2024

https://github.com/kigawas/mipscpu

A single cycle CPU running on Xilinx Spartan 6 XC6LX16-CS324, supporting 31 MIPS instructions.

educational-project mips verilog

Last synced: 10 Jan 2025

https://github.com/algosup/2024-2025-project-1-fpga-team-3

First project of the year 2024-2025

fpga frogger game verilog vga

Last synced: 16 Jan 2025

https://github.com/suda-morris/suda_riscv

Playing with FPGA and RISC-V

chisel3 fpga risc-v verilog

Last synced: 30 Dec 2024

https://github.com/harikrishnan669/verilog

KTU S4 DIGITAL LAB PROGRAMS (VERILOG)

cse ktu ktu-s4-cse verilog

Last synced: 27 Jan 2025

https://github.com/risto97/cascade_classifier

Python, C, RTL implementation of Viola Jones cascade classifier, using pretrained model from opencv.

face-detection fpga object-detection pygears python verilog viola-jones

Last synced: 21 Dec 2024

https://github.com/yaxsomo/iris_cubesat

This Repository is dedicated to FPGA development of the IRIS CubeSat

aerospace cubesat fpga free-space-optical-communiucation satellite verilog vhdl vivado xilinx

Last synced: 11 Jan 2025

https://github.com/muhammadtalhasami/rtl_practice

This repository contain basic verilog codes which include the implementation of DLD (digital logic desgin ) circuits.

100daysofrtl hardware-coding muhammadtalhasami-github- rtl testbench verilog verilog-practice vhdl

Last synced: 25 Dec 2024

https://github.com/acmachado14/circuitoscombinacionais

Circuitos Combinacionais em Verilog | Trabalho pratico pra disciplina de Introdução aos Sistemas Lógicos - UFV

verilog

Last synced: 21 Jan 2025

https://github.com/mgriebling/lola

A digital design language by Nicklaus Wirth, similar to VHDL and Verilog, but much simpler and easier to master.

circuit-compiler digital-circuit-design lola simulator swift verilog vhdl wirth

Last synced: 29 Dec 2024

https://github.com/chrnthnkmutt/carpark_verilog

This project is using for illustrating on making the circuit on Xillin's BASYS3 from AMD and Verilog Language on Vivado, on the scope of car parking system

basys3 basys3-fpga fpga verilog verilog-code verilog-project

Last synced: 14 Jan 2025

https://github.com/zazi2002/computer-architectur-lab

Computer Architecture Lab projects with various fundamental concepts, including multi-cycle MIPS processors and PIC32 microcontroller programming.

counter mips multicycle-processor pic32 verilog

Last synced: 28 Dec 2024

https://github.com/harshalmittal4/24-bit-risc-processor

Computer Architecture-MIPS Processor simulation in verilog with self developed ISA

isa risc-processor verilog

Last synced: 20 Jan 2025

https://github.com/valaphee/redsynth

Generate redstone circuits out of Verilog.

bukkit-plugin fpga minecraft redstone synthesis verilog

Last synced: 07 Jan 2025

https://github.com/blagojeblagojevic/vga_verilog

Implementation of a vga interface on a Basys 3 FPGA

fpga verilog

Last synced: 21 Dec 2024

https://github.com/engineersbox/cbox16-processor

Implementation of QuAC v1.0 ISA microarchitecture called CBox16

arm armv7 cbox16 cpu isa microarchitecture mips mipsiv quac verilog vhdl

Last synced: 27 Jan 2025

https://github.com/xtrinch/icestick-fpga-example

Example project for Lattice icestick fpga

fpga icestorm-toolchain verilog

Last synced: 21 Dec 2024

https://github.com/standardsemiconductor/veldt-blinker-verilog

VELDT blinker example with verilog

veldt verilog

Last synced: 11 Jan 2025

https://github.com/kkkaan/metu-ceng-thes

Some of the homeworks I have done at metu ceng.

bash c clingo cpp haskell java prolog python quantum-computing verilog

Last synced: 04 Jan 2025

https://github.com/liu42/pipeline

《计算机组成原理》课程设计，基于 MIPS 系统的流水线 CPU 设计

architecture computer-architecture course-project cpu fpga homework-project mips mips-architecture mips-processor pipeline verilog

Last synced: 23 Nov 2024

https://github.com/abtinz/logic-circuits-final-project

Aut Logic Circuits Finall Project Fall 1400

verilog

Last synced: 12 Jan 2025

https://github.com/sgq995/rc4-de0-nano-soc

It's a cryptoprocessor that implements de RC4 algorithm

de0-nano-soc fpga fpga-soc rc4 verilog

Last synced: 07 Jan 2025

https://github.com/zhb2000/computerorganizationexperiment

计算机组成与设计课程实验

computer-organization verilog

Last synced: 25 Dec 2024

https://github.com/hugech38/mips

🐢 用 Verilog 实现的单周期 MIPS 指令集的 CPU，并用它来计算斐波那契数。

cpu mips mips-architecture mips-instructions mips-processor verilog vhdl

Last synced: 21 Jan 2025

https://github.com/bucknalla/warc_fusesoc

WARC Open Fusesoc Cores Repository

hls ip migen open-cores verilog

Last synced: 09 Jan 2025

https://github.com/bucknalla/axis-interfacer

Extract AXI (Full, Lite and Stream) interfaces from Verilog source files

axi axi-lite axis verilog xilinx

Last synced: 09 Jan 2025

https://github.com/vitalyankh/open-fpga-tutorial

Open FPGA Tutorial

chisel fpga verilog

Last synced: 11 Jan 2025

https://github.com/a-bdellatif/frequencydivider

verilog code for frequency divider circuit implemented with verilog hdl

digital-design fpga frequency-divider hardware-description-language hdl verilog

Last synced: 03 Feb 2025

https://github.com/rambodrahmani/dalle_porte_and_or_not_al_sistema_calcolatore

Dalle Porte AND OR NOT Al Sistema Calcolatore. Un viaggio nel mondo delle reti logiche in campagnia del linguaggio Verilog.

altera boolean-algebra boolean-logic logic-gates modelsim verilog

Last synced: 29 Dec 2024

https://github.com/abdallahabusedo/cmp305-introduction-verilog

introduction to Verilog in Integrated Circuit Design And VLSI technology

verilog verilog-code verilog-hdl verilog-project

Last synced: 13 Dec 2024

https://github.com/euripedesrocha/tbpp

A simple test library for verilator

cpp fusesoc verilator verilog

Last synced: 28 Jan 2025

https://github.com/ain1084/dual_clock_buffer

Dual clock buffer for modules connected by valid-ready protocol

protocol-buffers verilog

Last synced: 20 Dec 2024

https://github.com/ain1084/serial_audio_encoder

Serial audio encoder

encoder i2s-audio verilog

Last synced: 20 Dec 2024

https://github.com/mat1g3r/csc258_final_project

CSC258 final project

verilog

Last synced: 23 Jan 2025

https://github.com/rosscomputerguy/slimproc

SlimProc is a 32-bit RISC instruction set

cpu-emulator fpga processor verilog

Last synced: 19 Jan 2025

https://github.com/ellisgl/addressable-debouncer-verilog

Addressable 8 SPDT debouncer in Verilog

cpld debounce debounce-button debouncing fpga verilog

Last synced: 19 Jan 2025

https://github.com/jn513/baby-risco-5

Multi-cycle RISC-V processor with RV32E implementation

riscv riscv32 riscv32e verilog verilog-hdl

Last synced: 15 Dec 2024

https://github.com/jn513/estudos_verilog

Exemplos feito em verilog para estudos

fpga fpga-programming hardware verilog verilog-code verilog-hdl

Last synced: 15 Dec 2024

https://github.com/rishabh-agarwal/cisc530-computersystemarchitecture

This repository contain HW and assignment for ComputerSystemArchitecture class at Harrisburg University

assignment cisc530 harrisburg homework kapila university verilog

Last synced: 28 Dec 2024

https://github.com/dyna-bytes/fisr

Specialized FPU for Fast Inverse Square Root Algorithm

floating-point fpu hardware-acceleration verilog

Last synced: 30 Jan 2025

https://github.com/drom/vpreproc

Verilog preprocessor bindings for Node.js

napi nodejs preprocessor verilog

Last synced: 18 Dec 2024

https://github.com/rauhul/ece385

Digital Systems Laboratory UIUC FA 2016

altera fpga quartus-prime systemverilog verilog

Last synced: 29 Jan 2025

https://github.com/tomarus/midirouter

CMOD-A7 FPGA MIDI Merger/Router/Switch.

fpga midi verilog

Last synced: 15 Dec 2024

https://github.com/adolbyb/vhdl-fpga-nexys-a7

A collection of code from CDA 4240C: Design of Digital System and Lab

artix-7 fpga hardware-description-language hdl nexys-a7 verilog vhdl xilinx-vivado

Last synced: 20 Jan 2025

https://github.com/dyna-bytes/fpga_winter_internship_2020

[Korea University Elementary Particle Physics Lab] Hardware control research using FPGA

fpga rtl verilog vhdl

Last synced: 30 Jan 2025

https://github.com/cmpark0126/mips_32bits

Implements 32bits MIPS with verilog. (18.11.25 ~ 18.12.)

fpga mips32cpu verilog

Last synced: 23 Dec 2024

https://github.com/wpmed92/takerisc

A RISC-V RV32I Core written in TL-Verilog

hardware riscv riscv32 tl-verilog verilog

Last synced: 03 Feb 2025

https://github.com/marialmeida1/study-ac

Atividades de Arquitetura de Computadores 1

arquitetura-de-computadores java python verilog

Last synced: 05 Jan 2025

https://github.com/bilalm04/combination-lock-fsm

Moore FSM combination lock in Verilog for DE1-SOC Board.

de1-soc hardware verilog

Last synced: 31 Dec 2024

https://github.com/andrejchoo/uart_spiflash_programmer_on_fpga

UART programmer SPI FLASH 25-series on FPGA or CPLD

fpga programmer spi-flash verilog

Last synced: 11 Dec 2024

https://github.com/pseudoincorrect/fpga_mcu_wifi

Link between a PC and a FPGA through wifi

c fpga socket verilog wifi

Last synced: 16 Dec 2024

https://github.com/tm90/verilogmodules

generic Verilog modules for reuse...

generic-verilog-modules systemverilog verilog

Last synced: 13 Jan 2025

https://github.com/sauravmaheshkar/verilog-template

❄️ Template for Verilog Projects using iverilog and gtkwave (nix devShell supported)

hardware-description-language template-project verilog verilog-template vhdl

Last synced: 01 Feb 2025

https://github.com/junzhengca/space-enemies

Rip off of space invaders coded in Verilog with VGA output support, intended for DE2-115 FPGA board. Final project for CSCB58.

assignment de2-115 hardware project verilog

Last synced: 13 Dec 2024

https://github.com/weisrc/fpgaudio

MIDI file to Verilog Code Generation - FPGAudio!

midi verilog

Last synced: 23 Dec 2024

https://github.com/pavlostzitzos/hdls-intro

SystemVerilog , Verilog , Verilog-A , Verilog-AMS tutorial

verilog verilog-hdl verilog-testbenches vhdl

Last synced: 24 Dec 2024

https://github.com/byte-me404/tt-ps2-morse-encoder

Custom ASIC design which decodes a PS/2 keyboard, furthermore it encodes and outputs the data as morse code

asic morse-code ps2-keyboard tinytapeout verilog

Last synced: 05 Jan 2025

https://github.com/xilover/iot-and-edge-computing

Hands-on learning experience in IoT, edge computing, and embedded systems using a variety of platforms such as microcontrollers (nRF, STM32, ESP32), FPGAs (Xilinx), and SoCs (Raspberry Pi, Zynq).

aws-iot azure-iot ble circuit-design edge-computing esp32 fpga iot mqtt nrf pynq-z2 raspberry-pi rtos stm32 system-on-chip verilog vhdl vivado xilinx xilinx-zynq

Last synced: 18 Dec 2024

https://github.com/alyssonmach/sistema-seguranca-residencial

Projeto final da disciplina Laboratório de Circuitos Lógicos - Sistema de Segurança Residencial.

logic-circuit logic-gates logisim project ufcg verilog

Last synced: 24 Dec 2024

https://github.com/calint/zen-x

experimental retro 16 bit cpu written in verilog xilinx vivado intended for fpga Cmod S7 from Digilent

16-bit cmod-s7 cpu fpga verilog vintage vivado xilinx

Last synced: 10 Jan 2025

https://github.com/sameer/de2-115-template

HDLMake template for terasIC DE2-115

de2-115 hdlmake template verilog vhdl

Last synced: 18 Dec 2024

https://github.com/tmahlburg/mriscv

simple, modular rv32i implementation (WIP)

risc-v riscv riscv32 rv32i verilog verilog-hdl

Last synced: 17 Jan 2025

https://github.com/tmahlburg/picosoc-basys3

Wrapper module for the PicoSoC to support the Digilent Basys 3

artix artix-7 basys3 digilent picorv32 picosoc risc-v verilog vivado xilinx

Last synced: 17 Jan 2025

https://github.com/sofiavalos/verilog_ethernet_10g_pcs

Bloques y bancos de pruebas PCS para Ethernet 10G.

ethernet pcs verilog

Last synced: 05 Jan 2025

https://github.com/the-pinbo/risc-spm

This project involves the development and enhancement of a RISC Stored-Program Machine (RISC SPM), based on the architecture detailed in "Advanced Digital Design with the Verilog HDL" by Michael D. Ciletti.

computer-architecture riscv verilog

Last synced: 25 Dec 2024

https://github.com/hiyouga/digic-experiment

BUAA CST Autumn 2018 Digital Circuit Experiment

digital-circuit verilog

Last synced: 05 Jan 2025

https://github.com/lemongrb/frequencydivider

verilog code for frequency divider circuit implemented with verilog hdl

digital-design fpga frequency-divider hardware-description-language hdl verilog

Last synced: 10 Jan 2025

https://github.com/kar-dim/icsd-digitalsystems

Some Verilog projects, implemented as part of my university coursework (2013-2019, Information and Communications Systems Engineering, University of the Aegean).

verilog

Last synced: 04 Jan 2025

https://github.com/francoriba/alu-uart-basys3

UART modules interface using Verilog for the Basys3 board (Digilent). Computer Architecture 2023. FCEFyN, UNC, Argentina

arquitectura-de-computadores basys3-fpga computerarchitecture fcefyn hardwaredescription uart unc verilog

Last synced: 11 Jan 2025

https://github.com/vgalovic/hdl_examples

A collection of VHDL and Verilog examples organized by language and practice section, with setup.tcl files for easy Vivado setup. These examples reflect my FPGA development practice and learning.

tcl verilog vhdl vivado

Last synced: 03 Jan 2025

https://github.com/vincent-g-van/one-time-pad-fpga

64-Bits One-Time Pad on FPGA Board (Nexys 4 DDR Artix-7).

diligent nexys4 one-time-pad otp seven-segment verilog vivado

Last synced: 30 Jan 2025

https://github.com/delhatch/flipdot_video

Video streaming from a camera to a 58x24 pixel flipdot display. See the two flipdot_display*.mp4 videos. All processing in Verilog RTL (no softcore uP).

altera de2-115 flipdot flipdots fpga verilog

Last synced: 13 Jan 2025

https://github.com/awrsha/digital-systems

Digital systems lesson with Dr. Vahid Rostami Provided by Qazvin Islamic Azad University

digital-systems-design verilog vhdl-examples

Last synced: 12 Jan 2025

https://github.com/mattjesc/uart-cdc-design

UART Design with CDC, FIFO Buffers, and Dynamic Baud Rate Configuration

cdc fifo fpga uart verilog vivado

Last synced: 18 Jan 2025

https://github.com/rithwikksvr/verilog-snake-game

Last semester we made a Snake Game implemented on Hardware. For this Purpose we used Basys 2 Spartan-3E FPGA, 7x5 LED Matrix and Verilog Programming.

fpga verilog

Last synced: 12 Jan 2025

https://github.com/amir78729/logical-circuits-course-final-project

My Logical Circuits course Final Project - Fall98(2019) - VERILOG

logical-circuits verilog

Last synced: 18 Jan 2025

https://github.com/eshansurendra/uart-fpga

This repository documents a project undertaken as part of the EN2111 Electronic Circuit Design module at the University of Moratuwa, focusing on the implementation of a UART communication link between two FPGA boards.

digital-design embedded-systems fpga quartus-prime systemverilog-hdl testbench uart verilog

Last synced: 18 Jan 2025

https://github.com/ellisgl/driver-yl-3

Verilog code to run the YL-3 8 digit 7 segment display.

seven-segment verilog

Last synced: 19 Jan 2025

https://github.com/mummanajagadeesh/i2c-protocol-verilog

Verilog Implementation of I2C Protocol using Finite State Machine (FSM) design

finite-state-machine fpga fsm i2c i2cprotocol verilog verilog-hdl verilog-project xilinx xilinx-vivado

Last synced: 25 Jan 2025

https://github.com/chayashri2308/parking_management

Parking Management System using Verilog, to identify the occupied and vacant space in a parking lot.

fpga verilog

Last synced: 31 Jan 2025

Verilog Awesome Lists
awesome-hdl 121 awesome-open-hardware-verification 44 ASIC-Design-Roadmap 83 VHDL-Guide 287 CPLD-Guide 287
Verilog Categories
OpenCL Tools, Libraries and Frameworks 138 C/C++ Tools, Libraries and Frameworks 80 C/C++ Learning Resources 68 MATLAB Tools, Libraries, Frameworks 66 Firmware Tools, Libraries, and Frameworks 56 Assembly Learning Resources 36 MATLAB Learning Resources 34 Meta HDL and Transpilers 32 Projects and IPs 31 Firmware Learning Resources 28 Verilog/SystemVerilog Learning Resources 25 Verilog/SystemVerilog Tools 24 Frameworks: 23 OpenCL Learning Resources 22 HLS 16 Tutorials and Courses 15 Tutorials and Courses 💬[Intro](./Tutorials%20and%20Courses/README.md) 15 PSS : Portable test and Stimulus Standard 14 Awesome Awesome ⭐ 12 HDL simulators and compilers 9