Projects in Awesome Lists tagged with vhdl

https://github.com/yantavares/risc-v-unicycle

Repository for RISC-V Unicycle Processor Implementation in VHDL and Course Material for 'Organization and Architecture of Computers' at UnB (2023/2)

processor risc-v vhdl

Last synced: 16 Dec 2024

https://github.com/kazhuu/audio-synthesizer

Copy of old FPGA audio synthesizer project for DE2 development board

audio fpga synthesizer vhdl vhdl-code

Last synced: 27 Dec 2024

https://github.com/pdsmart/tzpufusionx

tranZPUter FusionX - Software based physical Z80 replacement using a Linux System-on-a-module and a highly accurate Z80 Emulation written in C.

bash c cpld driver electronics kernel linux retro som vhdl

Last synced: 15 Oct 2024

https://github.com/mrtkp9993/vhdlexamples

VHDL examples.

embedded-software embedded-systems fpga vhdl vhdl-code

Last synced: 17 Nov 2024

https://github.com/chuckb/ghdl-interactive-sim

Interactive GHDL simulation of a VHDL adder using Python, Cocotb, and pygame

cocotb ghdl gui pygame python simulator vhdl vpi

Last synced: 20 Dec 2024

https://github.com/marph91/icestick-remote

Remote control in VHDL, which fits on a Lattice icestick.

fpga ghdl hardware ice40 icestick vhdl

Last synced: 07 Dec 2024

https://github.com/marph91/pocket-bnn

BNN-to-FPGA framework, written in VHDL and Python

bnn cnn cnn-architecture deep-learning fpga hardware image-processing larq python ulx3s vhdl

Last synced: 17 Oct 2024

https://github.com/rohankalbag/vlsi-design

VLSI Design - Autumn Semester 2022 - Indian Institute of Technology Bombay

brent-kung dadda-multiplier digital-logic-design multiply-accumulate ngspice vhdl vlsi-design

Last synced: 12 Nov 2024

https://github.com/kampi/zybo

Miscellaneous things and projects for my ZYBO and ZYNQ devices.

amd arm c cpp fpga fpga-programming linux vhdl wsl-ubuntu wsl2 xilinx zybo zynq

Last synced: 20 Nov 2024

https://github.com/nobodywasishere/upduino-projects

Various VHDL projects I've worked on for the Upduino v2.0 and v3.0

ghdl ghdl-yosys-plugin icestorm toolchain upduino upduino2 vhdl

Last synced: 20 Dec 2024

https://github.com/danielvieiravega/vcdparser

Value Change Dump (VCD) File

hdl simulations value-change-dump vcd verilog vhdl

Last synced: 15 Nov 2024

https://github.com/thelogicmaster/vhdlsonic

A custom 32-bit architecture, microcontroller, retro console, and software suite

cpu emulator fpga microcontroller retro-console rtos vhdl

Last synced: 09 Dec 2024

https://github.com/hukenovs/fp32_logic

Floating point FP32 core HDL. For Xilinx FPGAs. Include base converters and some math functions.

altera digital-signal-processing dsp floating-point fpga ieee-754 ieee754 integer-arithmetic verilog vhdl xilinx

Last synced: 19 Nov 2024

https://github.com/marph91/yaaes

Yet Another AES implementation in hardware.

aes cryptography fpga hardware python vhdl

Last synced: 17 Oct 2024

https://github.com/trcwm/fptool

Compiler for generating fixed-point logic using VHDL

arithmetic fixed-point hdl signal-processing vhdl

Last synced: 06 Nov 2024

https://github.com/bbn-q/aps2-comms

HDL modules for ethernet communications with APS2 and TDM modules

fpga-firmware vhdl

Last synced: 11 Nov 2024

https://github.com/yne/r3k

5 stages pipeline MIPS R3000

mips pipeline-cpu r3000 vhdl

Last synced: 17 Dec 2024

https://github.com/gergoerdi/clash-sandbox

Playing around with CLaSH

brainfuck clash cpu fpga hardware vhdl

Last synced: 16 Nov 2024

https://github.com/ana06/function-graphing-fpga

Team project developed on FPGA using VHDL: Function graphing.

fpga function-graph function-graphing ucm vhdl

Last synced: 06 Dec 2024

https://github.com/pdsmart/sharpmz

A Sharp MZ Series (80K,80C,1200,80A,80B,700,800,2000) Computer Hardware Emulation written in VHDL on Altera FPGA fabric. Runs on the MiSTer project and other Altera Cyclone devices.

assembly-language c cpp electronics emulator fpga perl retrocomputing vhdl

Last synced: 15 Oct 2024

https://github.com/HEP-SoC/SoCMake

CMake based hardware build system

asic build-automation build-system cmake fpga integrated-circuits system-on-chip systemverilog verilator verilog vhdl vhdl-language

Last synced: 27 Nov 2024

https://github.com/davidbrochart/bundle

FPGA-accelerated array computing

fpga numpy python vhdl xilinx

Last synced: 11 Oct 2024

https://github.com/nating/microprocessor

🎛 A Microcoded Instruction Set Processor. 🎛

microprocessor vhdl

Last synced: 02 Jan 2025

https://github.com/arxiver/pipelined-mips

MIPS Pipelined CPU simulation using VHDL language

hardware-designs processor processor-architecture processor-simulator vhdl vhdl-code

Last synced: 15 Nov 2024

https://github.com/davidbrochart/pyclk

Python implementation of a Hardware Description Language (HDL)

fpga hdl myhdl python verilog vhdl

Last synced: 11 Oct 2024

https://github.com/paebbels/pyversioning

Gather version information and export as any programming language source file for inclusion into compilation.

appveyor-ci c git github-workflows gitlab-ci python3 template-engine travis-ci version-control vhdl

Last synced: 08 Nov 2024

https://github.com/paebbels/picoblaze-examples

PicoBlaze-Examples offers reference and example designs for the PicoBlaze-Libary.

fpga picoblaze-library poc-library synthesis vhdl xilinx

Last synced: 07 Dec 2024

https://github.com/duartegalvao/arduzynq-tutorials

Simple tutorials for getting started with programming on Trenz ArduZynq boards.

arduino-shield arduzynq fpga fpga-board rtl te0723 trenz tutorial uart vhdl vivado vivado-hls xilinx zynq-7000 zynq-7010 zynq-example-project

Last synced: 18 Nov 2024

https://github.com/miranda1000/vivado_ps-pl_data_exchange

Creating a Custom IP for PS-PL data exchange in Vivado

digilent-zybo tutorial vhdl vitis vivado zybo-z7

Last synced: 14 Dec 2024

https://github.com/kazhuu/vhdl-examples

VHDL examples for a different kind of topics

example example-code example-codes example-project examples ghdl hdlcc modelsim vhdl vim vim-hdl

Last synced: 07 Nov 2024

https://github.com/markmll/tang_nano_as_shipped

A close approximation of the demo code on Sipeed Tang Nano boards as shipped.

fpga verilog vhdl

Last synced: 21 Dec 2024

https://github.com/choaib-elmadi/getting-started-with-vhdl

Getting started with VHDL: Very High Speed Integrated Circuit Hardware Description Language.

fpga fpga-programming hdl vhdl vhdl-code vhdl-examples

Last synced: 22 Nov 2024

https://github.com/rogermiranda1000/vivado_ps-pl_data_exchange

Creating a Custom IP for PS-PL data exchange in Vivado

digilent-zybo tutorial vhdl vitis vivado zybo-z7

Last synced: 27 Oct 2024

https://github.com/jc-ll/vertigo

VHDL'93 VHDL parser handwritten in Ruby

parse vhdl

Last synced: 15 Dec 2024

https://github.com/var7600/vhdl-generator

App that Generate VHDL Code and Testbench template file

vhdl vhdl-code vhdl-modules vhdl-testbench

Last synced: 07 Nov 2024

https://github.com/kampi/tinyavr

VHDL design of an AVR8 CPU.

avr cpu fpga mcu vhdl xilinx xilinx-fpga xilinx-vivado

Last synced: 20 Nov 2024

https://github.com/ghaiklor/arves

Another RISC-V Educational Softcore

risc-v vhdl

Last synced: 12 Dec 2024

https://github.com/chmoore889/fpga-correlator

A FPGA linear/multi-tau correlator written in VHDL.

correlator fpga vhdl

Last synced: 15 Nov 2024

https://github.com/stavros/fsm_caralarm

Finite-State Machine Design of a Simple Car Security Alarm on FPGA

finite-state-machine fpga fsm vhdl vhdl-code vhdl-examples

Last synced: 17 Nov 2024

https://github.com/raulmurillo/conga_22

Code for reproducing CoNGA 2022 results on posit arithmetic operators

computer-architecture computer-arithmetic floating-point posit vhdl

Last synced: 18 Dec 2024

https://github.com/djcopley/vga_module

VHDL VGA-Display Module

vga vhdl vhdl-modules

Last synced: 22 Dec 2024

https://github.com/sefakcmn00/fpga-vhdl-samples-

Simple logic gate applications were implemented using FPGA VHDL language. These are; counter counter circuit, float point, multix.

floating-point fpga verilog vhdl

Last synced: 14 Nov 2024

https://github.com/matozinho/neander

NEANDER - A basic theorical computer

hardware hardware-designs neander simulation vhd vhdl

Last synced: 17 Dec 2024

https://github.com/tirtharajsinha/vhdl_codes

vhdl

adder circuit-design diagram logic-gate-simulator logic-gates subtractor truth-table universal-gate vhdl vhdl-code

Last synced: 09 Nov 2024

https://github.com/shishir-dey/vhdl-samples

Contains VHDL netlists of basic digital circuits

hardware-designs netlist testbench vhdl

Last synced: 14 Nov 2024

https://github.com/jofrfu/haw-v

Fork of a RISC-V compliant CPU, which originated in a project at the HAW Hamburg

assembly c fpga linux risc-processor risc-v vhdl vivado xilinx-fpga

Last synced: 13 Nov 2024

https://github.com/brakmic/blinker2

A simple Hardware Design for Xilinx Spartan-6 FPGA written in VHDL

fpga vhdl

Last synced: 02 Jan 2025

https://github.com/lemurpwned/classic-fpga

basic simulations of digital electronics using vhdl

digital-electronics fpga signal simulation testbench vhdl vhdl-files

Last synced: 29 Dec 2024

https://github.com/bbn-q/vhdl-components

Bits and bobs for FPGA's firmware in VHDL

fpga-firmware vhdl

Last synced: 11 Nov 2024

https://github.com/alicepagano/collection-of-university-assignments

Collection of University assignments done during my Master degree in Physics of Data at the University of Padova.

fortran machinelearning many-body-physics nanocluster python quantum-computing r statistical-analysis vhdl vhdl-examples

Last synced: 22 Nov 2024

https://github.com/aasmundn/rsa-hw-accelerator

Hardware accelerator for RSA encryption and decryption written in VHDL.

ghdl rsa vhdl

Last synced: 14 Dec 2024

https://github.com/choaib-elmadi/working-with-fpga-and-mips

A collection of practical sessions exploring FPGA programming and MIPS-based systems using the ALTERA Cyclone V SoC DE-1 SoC board.

embedded-systems fpga fpga-board fpga-programming fpga-soc mips mips-architecture mips-assembly soc vhdl

Last synced: 29 Nov 2024

https://github.com/choaib-elmadi/working-with-fpga-and-vhdl

A collection of practical FPGA and VHDL projects using the ALTERA Cyclone V SoC DE-1 SoC board.

electronics embedded-systems fpga fpga-board fpga-programming fpga-soc soc system-on-chip vhdl vhdl-code

Last synced: 29 Nov 2024

https://github.com/muhammadtalhasami/rv32i_single_cycle

This repository contains an implementation of a RV32I fetch pipeline microprocessor. The RV32I is a 32-bit RISC-V instruction set architecture, with the 'I' extension indicating the base integer instructions.

fetch-stage-pipeline gtkwave hardware-designs muhammadtalhasami-github- pipeline-processor risc-v-assembly risc-v-pipeline risc-v-processor risc-v-processor-images rv32i rv32i-processor single-cycle-processor single-cycle-processor-gtkwave-image system-verilog system-verilog-codes verilator verilog verilog-code-examples verilog-codes vhdl

Last synced: 25 Dec 2024

https://github.com/diegolonio/escom

Todo el código (casi) que he escrito para las unidades de aprendizaje de la Escuela Superior de Cómputo (IPN).

adoo bison c-language c-programming-language compiler-design compilers computer-architecture data-structures escom ipn java linux operating-system php python sistemas-operativos ubuntu vhdl web

Last synced: 12 Oct 2024

https://github.com/ryanfleck/projects

Anything that doesn't belong to a specific development effort ends up here.

c c-sharp cpp go java js latex lisp prolog python ruby scala vhdl

Last synced: 18 Oct 2024

https://github.com/facthunder/understand

Docker image for SciTools Understand

analyzer c code-analysis docker docker-image java python scitools scitools-understand static-analysis understand vhdl

Last synced: 13 Dec 2024

https://github.com/blaz-r/fpga-neopixel

FPGA module for NeoPixel led-strip written in VHDL. Works with ws2812b (RGB) and sk6812 (RGBW).

fpga neopixel rgb-led sk6812 vhdl ws2812

Last synced: 25 Dec 2024

https://github.com/pdsmart/mz80a_rfs

A Sharp MZ80A Rom Filing System - a complete hardware/software upgrade replacing the Monitor & User ROMs with 2MB Flash, SD Card and upgraded firmware. Project uses C and Z80 Assembler.

assembly-language bash cpm electronics retrocomputing vhdl

Last synced: 05 Dec 2024

https://github.com/pdsmart/mz80a_80colour

A Sharp MZ80A Video upgrade. v1.0 allows switchable 40/80 column display with colour monitor output, v2.0 provides full pixel graphics compatible with the MZ80B.

cpld electronics fpga kicad mz80a vhdl

Last synced: 05 Dec 2024

https://github.com/markus-k/rv32-soc

A simple RISC-V SoC based on picorv32

cpu fpga mojov3 risc-v riscv riscv-soc soc spartan6 vhdl xilinx xilinx-fpga

Last synced: 21 Nov 2024

https://github.com/jeffdecola/my-masters-thesis

A High-Level Design Framework Illustrating Technology Migration.

fpga hdl masters-degree masters-thesis technology-migration thesis vhdl

Last synced: 13 Dec 2024

https://github.com/delpineai/7segmentdisplay

7-Segment Alphanumeric Display using VHDL. Programmed with pure Boolean algebra.

7segment alphanumeric alphanumeric-display boolean boolean-algebra boolean-logic coding logic-gates programming vhdl vivado

Last synced: 19 Dec 2024

https://github.com/jiegec/vfloat

Mirror of https://coe.northeastern.edu/Research/rcl/projects/floatingpoint/index.html

fpu vfloat vhdl

Last synced: 14 Dec 2024

https://github.com/amir78729/computer-architecture-lab

Computer Architecture Lab (summer 99)

computer-architecture vhdl

Last synced: 17 Nov 2024

https://github.com/imciner2/hdl_library

Various HDL components and tools

fpga vhdl

Last synced: 29 Nov 2024

https://github.com/podorozhny/isa-parallel-port-adapter

VHDL, ISA, LPT (IEEE 1284, Parallel Port) in compatibility mode (SPP)

ieee-1284 isa lpt parallel-port spp vhdl

Last synced: 13 Nov 2024

https://github.com/qnighy/ghdl-hello

GHDL Sample Program & Makefile

ghdl vhdl

Last synced: 13 Dec 2024

https://github.com/suvraneel/vhdl-xilinx

Projects were generated in Xilinx v14.7 If you're using Xilinx you may simply import the projects. Otherwise just read the codes in .vhd extensioned files. ☮️

vhdl vhdl-code xilinx

Last synced: 10 Nov 2024

https://github.com/var7600/vhdl-testbench

A simple python script to generate a VHDL testbench template given an entity-architecture declaration passed as argument(s) as a file(s)

vhdl vhdl-testbench

Last synced: 07 Nov 2024

https://github.com/meetps/ee-214

VHDL and Verilog Codes for Digital Lab.

digital-logic fpga verilog vhdl

Last synced: 09 Nov 2024

https://github.com/fancellu/vhdl_basys3_pwm_7_segment

Basys 3 FPGA with 7 segment display, switch and led

fpga vhdl

Last synced: 10 Nov 2024

https://github.com/stavros/ledtoggle

An example for NIOS II processor to toggle a Led with a Button

c fpga nios-ii vhdl vhdl-code

Last synced: 17 Nov 2024

https://github.com/stavros/4bitcounterparload

A 4bit Counter with Parallel Load including a Clock Divider and a BCD decoder

bcd counter fpga vhdl vhdl-code vhdl-examples

Last synced: 17 Nov 2024

https://github.com/tremeschin/my-first-vhdl-even-or-odd

Blazing fast Even or Odd VHDL library

joke vhdl vhdl-code vhdl-testbench

Last synced: 11 Nov 2024

https://github.com/marph91/icestick-uart

Lightweight UART implementation in VHDL for the lattice icestick

fpga ghdl hardware ice40 icestick uart vhdl yosys

Last synced: 07 Dec 2024

https://github.com/stavros/multiplier4bit

A 4bit Multiplier in VHDL

fpga full-adder half-adder vhdl vhdl-code vhdl-examples

Last synced: 17 Nov 2024

https://github.com/sinakarvandi/hardware-design-stack

The source codes used in the blog post available at: https://rayanfam.com/topics/hardware-design-stack/

asic asic-design chisel chisel3 fpga gtkwave modelsim netlist openlane openram verilator verilog vhdl vitis vitis-hls vivado vivado-hls

Last synced: 17 Nov 2024

https://github.com/engineeringsoftware/hdlp

Code and data for "On the Naturalness of Hardware Descriptions" in ESEC/FSE'20

deep-learning hardware-description-language machine-learning naturalness pytorch systemverilog verilog vhdl

Last synced: 18 Nov 2024

https://github.com/amamory/hermes-trojan

Example of hardware trojan in a router detected with formal property verification

assertions formal-verification network-on-chip property-based-testing sva systemverilog trojan vhdl

Last synced: 21 Nov 2024

https://github.com/amamory/axis_s_led_ip

A Vivado IP to connect LEDs to a slave AXI streaming interface

axi4 tcl vhdl vivado

Last synced: 21 Nov 2024

https://github.com/shyamal-anadkat/the-11-of-us

adc ece551 flight-controller hdl integrator quadcopter synthesis system-verilog uart verilog vhdl

Last synced: 16 Dec 2024

https://github.com/david-palma/mips-32bit

Microprocessor without Interlocked Pipelined Stages (MIPS) architectures

32-bit c education mips mips-architecture mips-assembly multi-cycle single-cycle vhdl

Last synced: 04 Dec 2024

https://github.com/hanshuebner/microcore-xilinx

microCore adapted to Xilinx FPGAs

forth fpga vhdl

Last synced: 25 Dec 2024

https://github.com/rezamardanidev/morrismano_basiccomputer_vhdl

A VHDL implementation of the Morris Mano Basic Computer, including all key components such as registers, memory, ALU, control unit, and a common bus, designed for educational purposes. Fully modular and ready for simulation.

basic-computer computer mano morris morris-mano vhdl