Ecosyste.ms: Awesome

https://github.com/logisim-evolution/logisim-evolution

Digital logic design tool and simulator

circuit circuits digital-circuit digital-circuits digital-logic digital-logic-design education fpga logic logisim logisim-evolution simulator timing-diagram verilog vhdl

Last synced: 14 Jan 2025

https://github.com/spinalhdl/vexriscv

A FPGA friendly 32 bit RISC-V CPU implementation

cpu fpga riscv soc softcore spinalhdl verilog vhdl

Last synced: 16 Jan 2025

https://github.com/SpinalHDL/VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation

cpu fpga riscv soc softcore spinalhdl verilog vhdl

Last synced: 25 Oct 2024

https://github.com/ghdl/ghdl

VHDL 2008/93/87 simulator

compiler gcc ghdl hacktoberfest hardware llvm simulator testbench vhdl

Last synced: 14 Jan 2025

https://github.com/cocotb/cocotb

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

python test uvm verification verilog vhdl

Last synced: 14 Jan 2025

https://github.com/spinalhdl/spinalhdl

Scala based HDL

fpga rtl scala verilog vhdl

Last synced: 16 Jan 2025

https://github.com/SpinalHDL/SpinalHDL

Scala based HDL

fpga rtl scala verilog vhdl

Last synced: 26 Oct 2024

https://github.com/clash-lang/clash-compiler

Haskell to VHDL/Verilog/SystemVerilog compiler

asic fpga hardware-description-language haskell systemverilog verilog vhdl

Last synced: 16 Jan 2025

https://github.com/stnolting/neorv32

:rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

asic asip cpu embedded fpga gdb microcontroller neorv32 openocd processor risc-v riscv rtl rv32 safety soc soft-core system-on-chip verilog vhdl

Last synced: 27 Oct 2024

https://github.com/olofk/fusesoc

Package manager and build abstraction tool for FPGA/ASIC development

eda fpga package-manager python reuse verilog vhdl

Last synced: 15 Jan 2025

https://github.com/VUnit/vunit

VUnit is a unit testing framework for VHDL/SystemVerilog

asic fpga systemverilog-hdl testbench unit-testing universal-verification-methodology verification verilog-hdl vhdl

Last synced: 09 Nov 2024

https://github.com/open-sdr/openwifi-hw

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

ad9361 analog-devices csma dma fpga hardware hls ieee80211 linux mac80211 ofdm rtl sdr software-defined-radio verilog vhdl wi-fi xilinx zynq

Last synced: 15 Jan 2025

https://github.com/antonblanchard/microwatt

A tiny Open POWER ISA softcore written in VHDL 2008

openpower ppc64le processor vhdl

Last synced: 28 Nov 2024

https://github.com/olofk/edalize

An abstraction library for interfacing EDA tools

altera eda fossi fpga ghdl icarus-verilog icestorm lattice modelsim riviera-pro simulation spyglass synthesis systemverilog verilator verilog vhdl vivado xilinx yosys

Last synced: 16 Jan 2025

https://github.com/sergeykhbr/riscv_vhdl

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

cpu debugger qt riscv simulator soc systemc vhdl

Last synced: 10 Nov 2024

https://github.com/JulianKemmerer/PipelineC

A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

c fpga fpga-acceleration fpga-accelerators fpga-programming hardware hardware-description hardware-description-language high-level-synthesis hls open-source-hardware pipelines python vhdl

Last synced: 09 Nov 2024

https://github.com/nickg/nvc

VHDL compiler and simulator

compiler fpga simulator vhdl

Last synced: 26 Oct 2024

https://github.com/VLSI-EDA/PoC

IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

altera asic fpga hardware-designs hardware-libraries hardware-modules lattice osvvm poc-library python regression-testing simulation synthesis testbenches uvvm verification vhdl vlsi vunit xilinx

Last synced: 10 Nov 2024

https://github.com/TerosTechnology/vscode-terosHDL

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

fpga systemverilog verilog vhdl

Last synced: 09 Nov 2024

https://github.com/jofrfu/tinytpu

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

assembly embedded-systems fpga fpga-accelerator hardware-acceleration hardware-architectures hardware-description-language hardware-designs internet-of-things iot ip-core linux tensor tensorflow tpu verilog vhdl vivado xilinx zynq

Last synced: 14 Jan 2025

https://github.com/Nuand/bladeRF-wiphy

bladeRF-wiphy is an open-source IEEE 802.11 compatible software defined radio VHDL modem

80211 bladerf dsss hdl ofdm ofdm-wireless-communications rtl vhdl

Last synced: 29 Oct 2024

https://github.com/slaclab/surf

A huge VHDL library for FPGA development

asic firmware fpga hdl python vhdl

Last synced: 15 Jan 2025

https://github.com/howerj/forth-cpu

A Forth CPU and System on a Chip, based on the J1, written in VHDL

c cpu forth fpga processor simulator softcore target-board vhdl

Last synced: 30 Oct 2024

https://github.com/VHDL-LS/rust_hdl

language-server parser rust-programming-language vhdl vhdl-language-server vhdl-parser

Last synced: 26 Oct 2024

https://github.com/nic30/hdlconvertor

Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4

antrl4 fpga parser python systemverilog systemverilog-parser verilog verilog-parser vhdl vhdl-parser

Last synced: 17 Jan 2025

https://github.com/Nic30/hdlConvertor

Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4

antrl4 fpga parser python systemverilog systemverilog-parser verilog verilog-parser vhdl vhdl-parser

Last synced: 26 Oct 2024

https://github.com/rggen/rggen

Code generation tool for configuration and status registers

amba apb asic axi csr eda fpga ral register-descriptions rtl soc systemverilog uvm uvm-ral-model uvm-register-model verilog vhdl wiki-documents wishbone-bus

Last synced: 26 Oct 2024

https://github.com/DegateCommunity/Degate

A modern and open-source cross-platform software for chips reverse engineering.

chips cpp cross-platform cybersecurity gui multi-platform reverse-engineering security security-tools verilog vhdl vlsi

Last synced: 18 Nov 2024

https://github.com/OSVVM/OSVVM

OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...

alerts constrained-random coverage coverage-bins memory memory-model methodology osvvm osvvm-blog scoreboard simulation testbench transaction-interfaces verification verification-methodologies vhdl

Last synced: 18 Nov 2024

https://github.com/nic30/hwt

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

codegen codegenerator compiler fpga hcl hls rtl simulator systemc systemverilog uvm verilog vhdl

Last synced: 18 Jan 2025

https://github.com/stnolting/neo430

:computer: A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.

customizable fpga gcc microcontroller msp430 msp430-gcc open-source processor soc soft-core system-on-chip vhdl

Last synced: 10 Nov 2024

https://github.com/Nic30/hwt

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

codegen codegenerator compiler fpga hcl hls rtl simulator systemc systemverilog uvm verilog vhdl

Last synced: 26 Oct 2024

https://github.com/kevinpt/symbolator

HDL symbol generator

hdl symbol verilog vhdl

Last synced: 15 Jan 2025

https://github.com/apertus-open-source-cinema/axiom-firmware

AXIOM firmware (linux image, gateware and software tools)

apertus axiom-beta axiom-cameras boot camera firmware gateware hacktoberfest hardware linux openhardware qemu u-boot vhdl

Last synced: 29 Oct 2024

https://github.com/fabioperez/space-invaders-vhdl

Space Invaders game implemented with VHDL

fpga games hardware vhdl

Last synced: 23 Dec 2024

https://github.com/OSVVM/AXI4

AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components

axi4 axi4-lite axi4-stream osvvm simulation simulation-modeling testbench tlm verification verification-component vhdl vip

Last synced: 26 Oct 2024

https://github.com/wfjm/w11

PDP-11/70 CPU core and SoC

fpga pdp-11 pdp11 retrocomputing vhdl

Last synced: 30 Nov 2024

https://github.com/howerj/bit-serial

A bit-serial CPU written in VHDL, with a simulator written in C.

16-bit 16-bit-cpu 1bit bit-serial cpu forth tiny vhdl

Last synced: 18 Jan 2025

https://github.com/OpenResearchInstitute/dvb_fpga

RTL implementation of components for DVB-S2

bch-fec dvb-s2 fpga hacktoberfest ldpc-codes vhdl

Last synced: 10 Nov 2024

https://github.com/yne/vcd

VCD file (Value Change Dump) command line viewer

cli gtkwave vcd vhdl

Last synced: 30 Oct 2024

https://github.com/inmcm/simon_speck_ciphers

Implementations of the Simon and Speck Block Ciphers

block-ciphers c cipher-s cryptography decryption encryption fpga nsa python security vhdl

Last synced: 27 Oct 2024

https://github.com/ben-marshall/verilog-vcd-parser

A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.

parser simulation systemverilog trace vcd verilog vhdl

Last synced: 29 Nov 2024

https://github.com/Paebbels/pyVHDLParser

Streaming based VHDL parser.

language-model parser python-3 vhdl

Last synced: 26 Oct 2024

https://github.com/paebbels/pyvhdlparser

Streaming based VHDL parser.

language-model parser python-3 vhdl

Last synced: 11 Jan 2025

https://github.com/paebbels/json-for-vhdl

A JSON library implemented in VHDL.

fileformat fpga ghdl json lattice modelsim parser questasim simulation synthesis vhdl xilinx

Last synced: 01 Nov 2024

https://github.com/hukenovs/intfftk

Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.

altera cooley-tukey-fft digital-signal-processing dsp fast-convolutions fast-fourier-transform fft fpga integer-arithmetic radix-2 route-optimization verilog vhdl vivado xilinx

Last synced: 19 Nov 2024

https://github.com/halfmanhalftaco/fpga-docker

Tools for running FPGA vendor toolchains with Docker

altera fpga lattice quartus verilog vhdl xilinx

Last synced: 06 Nov 2024

https://github.com/cocotb/cocotb-bus

Pre-packaged testbenching tools and reusable bus interfaces for cocotb

bus cocotb hdl interface testbench verilog vhdl

Last synced: 19 Jan 2025

https://github.com/johnlon/spam-1

Home Brew 8 Bit CPU Hardware Implementation including a Verilog simulation, an assembler, a "C" Compiler and this repo also contains my research and learning. See also the Hackaday.IO project. https://hackaday.io/project/166922-spam-1-8-bit-cpu

8bit alu assembler cmos cpu design homebrew-cpu logism rom ttl verilog verilog-components vhdl

Last synced: 16 Nov 2024

https://github.com/1995parham-learning/learning

@elahe-dastan / @1995parham training and testing repository :books: :nerd_face:

bash c go julia rust sml vhdl

Last synced: 17 Nov 2024

https://github.com/SpinalHDL/SpinalCrypto

SpinalHDL - Cryptography libraries

aes crc crypto cryptography des fpga hmac md5 rtl scala sha spinalhdl verilog vhdl

Last synced: 09 Nov 2024

https://github.com/spinalhdl/spinalcrypto

SpinalHDL - Cryptography libraries

aes crc crypto cryptography des fpga hmac md5 rtl scala sha spinalhdl verilog vhdl

Last synced: 16 Jan 2025

https://github.com/hukenovs/fp23fftk

Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL).

altera chirp convolution convolution-filter cooley-tukey-fft digital-signal-processing dsp fast-convolutions fast-fourier-transform fft floating-point fpga frequency-analysis ieee754 matlab octave radix-2 verilog vhdl xilinx

Last synced: 19 Nov 2024

https://github.com/OSVVM/OsvvmLibraries

Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.

osvvm verification vhdl

Last synced: 26 Oct 2024

https://github.com/MJoergen/HyperRAM

Portable HyperRAM controller

altera artix avalon fpga hyperram intel lattice modelsim quartus questa questasim vhdl vivado xilinx

Last synced: 10 Nov 2024

https://github.com/ghdl/docker

Scripts to build and use docker images including GHDL

actions ci dockerfiles ghdl gtkwave hardware icestorm nextpnr openocd pnr prjtrellis simulation synthesis testbench verilog vhdl vunit yosys

Last synced: 20 Dec 2024

https://github.com/nic30/hwtlib

hardware library for hwt (= ipcore repo)

fpga hardware-designs rtl verilog vhdl

Last synced: 15 Jan 2025

https://github.com/Nic30/hwtLib

hardware library for hwt (= ipcore repo)

fpga hardware-designs rtl verilog vhdl

Last synced: 09 Nov 2024

https://github.com/paebbels/picoblaze-library

The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a Chip (SoC or SoFPGA).

assembler fpga hardware hardware-architectures hardware-designs hardware-libraries hdl picoblaze-devices picoblaze-library poc-library simulation soc synthesis verilog vhdl

Last synced: 08 Nov 2024

https://github.com/Archfx/FPGA-stereo-Camera-Basys3

Integration of two camera 📷 modules to Basys 3 FPGA

fpga verilog vhdl

Last synced: 26 Oct 2024

https://github.com/nic30/hdlconvertorast

Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator

codegen codegenerator fpga python systemc systemverilog verilog vhdl

Last synced: 14 Jan 2025

https://github.com/bbn-q/vhdl-jesd204b

JESD204b modules in VHDL

jesd204b vhdl

Last synced: 10 Jan 2025

https://github.com/mbuesch/crcgen

Generator for CRC HDL code (VHDL, Verilog, MyHDL)

crc crc-algorithms crc-calculation crc32 myhdl verilog vhdl

Last synced: 31 Oct 2024

https://github.com/richjyoung/vscode-modern-vhdl

Modern VSCode VHDL Support

vhdl vhdl08 vhdl93 vscode vscode-language

Last synced: 07 Nov 2024

https://github.com/stnolting/neorv32-riscof

✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.

ghdl isa neorv32 processor risc-v riscof riscv sail-riscv verification vhdl

Last synced: 09 Nov 2024

https://github.com/nobodywasishere/vhdlref

A usable language reference for VHDL that is concise, direct, and easy to understand.

reference vhdl website

Last synced: 20 Dec 2024

https://github.com/nic30/hwthls

LLVM based HLS library for HWToolkit (hardware devel. toolkit)

compiler fpga hls llvm systemverilog verification verilog vhdl

Last synced: 16 Nov 2024

https://github.com/hukenovs/math

Useful m-scripts for DSP (CIC, FIR, FFT, Fast convolution, Partial Filters etc.)

cic digital-signal-processing dsp fast-convolutions fast-fourier-transform fft fir fpga m-scripts math matlab octave verilog vhdl

Last synced: 19 Nov 2024

https://github.com/nobodywasishere/vhdlproc

VHDLproc is a VHDL preprocessor

preprocessing python vhdl vhdl-preprocessor

Last synced: 20 Dec 2024

https://github.com/chaseruskin/orbit

An agile package manager and extensible build tool for HDLs

agile agile-development build-tool command-line-tool cross-platform hardware hdl package-manager systemverilog verilog vhdl

Last synced: 14 Nov 2024

https://github.com/hdl-registers/hdl-registers

An open-source HDL register code generator fast enough to run in real time.

asic axi axi-lite c cplusplus csr eda fpga generator html python register register-interface rtl vhdl

Last synced: 19 Jan 2025

https://github.com/marph91/pico-png

PNG encoder, implemented in VHDL

deflate fpga hardware huffman lzss png png-encoder python vhdl

Last synced: 08 Nov 2024

https://github.com/blangos/vexriscv_with_hw-gdb_server

VexRiscV system with GDB-Server in Hardware

c-language fpga-soc gdbserver microcontroller risc-v rsp vexriscv vhdl wishbone

Last synced: 12 Oct 2024

https://github.com/raulmurillo/flo-posit

Posit Arithmetic Cores generated with FloPoCo

adder flopoco multiplier posit posit-arithmetic unum vhdl

Last synced: 18 Dec 2024

https://github.com/marph91/pocket-cnn

CNN-to-FPGA-framework for small CNN, written in VHDL and Python

cnn cnn-architecture deep-learning fpga fully-convolutional-networks hardware image-processing onnx python vhdl

Last synced: 08 Nov 2024

https://github.com/aletempiac/des-cracker

DES cracking machine on FPGA

cracking des driver fpga synthesis vhdl zybo

Last synced: 09 Dec 2024

https://github.com/tabrizian/cache

Simple implementation of cache using VHDL

cache ram vhdl

Last synced: 13 Dec 2024

https://github.com/smithros/kpi-stuff

Some of my laboratories work in KPI and stuff connected with it.

ada android asm bigdata computer-engineering cpp cs hadoop java kpi kpi-ua masm32 ntuu-kpi parrallel-computing python realtime-system security system-programming vhdl

Last synced: 23 Oct 2024

https://github.com/salvatorebarone/cnn-vhdl

A library of VHDL components for Neural Networks

approximate-algorithms approximate-computing approximation artificial-intelligence artificial-neural-networks convolutional-neural-networks ghdl lenet-5 vhdl virtex xilinx-fpga

Last synced: 18 Oct 2024

https://github.com/delhatch/vga_mem_mapped

Memory-mapped VGA display for Xilinx/Zynq/Zedboard, with demo code for using it.

mandelbrot vga vhdl zedboard

Last synced: 13 Jan 2025

https://github.com/chaseruskin/legohdl

An experimental package manager and development tool for Hardware Description Languages (HDL).

digital-design digital-logic fpga hardware-description-language hardware-design hdl package-manager verilog vhdl

Last synced: 14 Nov 2024

https://github.com/aaronerhardt/qfsm

Official repsitory of Qfsm, a graphical Finite State Machine (FSM) designer

appimage cpp finite-state-machine qt state-diagrams vhdl

Last synced: 13 Oct 2024

https://github.com/chaseruskin/legoHDL

An experimental package manager and development tool for Hardware Description Languages (HDL).

digital-design digital-logic fpga hardware-description-language hardware-design hdl package-manager verilog vhdl

Last synced: 17 Nov 2024

https://github.com/jbush001/waveview

Digital Waveform Viewer

tool verilog vhdl waveform

Last synced: 15 Oct 2024

https://github.com/wavedrom/doppler

Doppler effect on WaveForms

hacktoberfest verilog vhdl

Last synced: 09 Nov 2024

https://github.com/benitoss/cyclonev_unamiga_v2

Cyclone V FPGA board for UnAmiga project with new addon 6 Buttons Megadrive Joystick

verilog vhdl

Last synced: 24 Dec 2024

https://github.com/avestura/pingponggame_cad_vga

🏓 A Ping Pong game written in VHDL with VGA support

cad computer-aided-design game guilan-university hardware intel ping-pong ping-pong-game quartus university vga vhdl

Last synced: 13 Jan 2025

https://github.com/clarkfieseln/fpga_hw_sim_fwk

FPGA Hardware Simulation Framework

api emulation emulator fpga fpga-programming hdl pyqt pyqt5 python python-3 python3 simulation simulator vhdl vhdl-code

Last synced: 10 Nov 2024

https://github.com/nobodywasishere/logidiff

A website and Python library for determining if two logical statements are equivalent. Uses VHDL syntax and logical operators.

brython logical-operators vhdl

Last synced: 20 Dec 2024

https://github.com/emsec/hal-benchmarks

Benchmark suite for HAL

hardware netlist reverse-engineering verilog vhdl

Last synced: 11 Jan 2025

https://github.com/zerebos/vhdl-communications

Example code showing different communications such as TTL, SPI and I2C.

7-segment fpga i2c-controller i2c-master i2c-protocol serial-communication spi-communication state-machine vhdl zackrauen-com

Last synced: 21 Dec 2024

https://github.com/hukenovs/adc_configurator

ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)

adc adc-configurator altera analog-signals cic dac ddc ddr dds digital-signal-processing dsp fir jesd204b serdes-mode serial-interface vhdl xilinx

Last synced: 19 Nov 2024

https://github.com/clarkfieseln/fpga_hw_sim_fwk_2

FPGA Hardware Simulation Framework

api emulation emulator fpga fpga-programming hdl pygubu pygubu-designer python python-3 python3 simulation simulator vhdl vhdl-code windows windows-10 windows-11 windows10

Last synced: 10 Nov 2024

https://github.com/lionleaf/dmkonst

An optimized pipelined MIPS CPU written in VHDL

processor vhdl

Last synced: 23 Dec 2024

https://github.com/areberoto/image-conv-vhdl

Implementation of a 2D Convolution Filter using VHDL for FPGAs.

convolution fpga image-processing rtl vhdl

Last synced: 04 Jan 2025

https://github.com/himewel/yolowell

A set of hardware architectures to build a co-design of convolutional neural networks inference at FPGA devices

darknet vhdl

Last synced: 09 Nov 2024

https://github.com/hukenovs/blackman_harris_win

Blackman-Harris Window functions (3-, 5-, 7-term etc.) from 1K to 64M points based only on LUTs and DSP48s FPGA resources. Main core - CORDIC like as DDS (sine / cosine generator)

cordic cordic-algorithm cosine dds digital-signal-processing dsp fpga hamming-window hann-window impulse-response kaiser-window matlab octave sine spectral-analysis taylor-method taylor-series verilog vhdl window-function

Last synced: 19 Nov 2024

https://github.com/jc-ll/ruby_rtl

Describing RTL circuit in Ruby

digital-circuits dsl hdl migen vhdl

Last synced: 15 Dec 2024

https://github.com/kazhuu/audio-synthesizer

Copy of old FPGA audio synthesizer project for DE2 development board

audio fpga synthesizer vhdl vhdl-code

Last synced: 27 Dec 2024

https://github.com/pdsmart/tranzputer

A transformable CPU, one version using FPGA technology and another using an ARM Cortex-M4 (K64F) to upgrade venerable Z80 systems in-situ. Project uses VHDL, C/C++, ARM, ZPU & Z80 Assembler.

bash c cpp electronics fpga vhdl

Last synced: 15 Oct 2024